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Merge pull request #11980 from jeromecoutant/PR_L4R9I
DISCO_L4R9I: update clock configuration for all clock sources
2 parents 24c6c4c + 354913a commit 48f544f

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2 files changed

+74
-132
lines changed

2 files changed

+74
-132
lines changed

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c

Lines changed: 72 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
/* mbed Microcontroller Library
2-
* Copyright (c) 2006-2017 ARM Limited
2+
* Copyright (c) 2006-2019 ARM Limited
3+
* Copyright (c) 2006-2019 STMicroelectronics
4+
* SPDX-License-Identifier: Apache-2.0
35
*
46
* Licensed under the Apache License, Version 2.0 (the "License");
57
* you may not use this file except in compliance with the License.
@@ -33,21 +35,12 @@
3335
#include "stm32l4xx.h"
3436
#include "mbed_assert.h"
3537

36-
/*!< Uncomment the following line if you need to relocate your vector Table in
37-
Internal SRAM. */
38-
/* #define VECT_TAB_SRAM */
39-
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
40-
This value must be a multiple of 0x200. */
41-
42-
4338
// clock source is selected with CLOCK_SOURCE in json config
4439
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
45-
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
40+
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X2 on board)
4641
#define USE_PLL_HSI 0x2 // Use HSI internal clock
4742
#define USE_PLL_MSI 0x1 // Use MSI internal clock
4843

49-
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
50-
5144
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
5245
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
5346
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
@@ -64,12 +57,10 @@ uint8_t SetSysClock_PLL_MSI(void);
6457
/**
6558
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
6659
* AHB/APBx prescalers and Flash settings
67-
* @note This function should be called only once the RCC clock configuration
68-
* is reset to the default reset state (done in SystemInit() function).
60+
* @note This function is called in mbed_sdk_init() and hal_deepsleep() functions
6961
* @param None
7062
* @retval None
7163
*/
72-
7364
void SetSysClock(void)
7465
{
7566
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
@@ -99,11 +90,6 @@ void SetSysClock(void)
9990
}
10091
}
10192
}
102-
103-
// Output clock on MCO1 pin(PA8) for debugging purpose
104-
#if DEBUG_MCO == 1
105-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
106-
#endif
10793
}
10894

10995
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
@@ -114,85 +100,56 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
114100
{
115101
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
116102
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
117-
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
118-
119-
// Used to gain time after DeepSleep in case HSI is used
120-
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
121-
return 0;
122-
}
103+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
123104

124-
// Select MSI as system clock source to allow modification of the PLL configuration
125-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
126-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
127-
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
105+
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
106+
{
107+
return 0; // FAIL
108+
}
128109

129110
// Enable HSE oscillator and activate PLL with HSE as source
130-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
111+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
131112
if (bypass == 0) {
132-
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
113+
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 16 MHz xtal on OSC_IN/OSC_OUT
133114
} else {
134-
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
115+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 16 MHz clock on OSC_IN
135116
}
136117
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
137-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
118+
#if DEVICE_USBDEVICE
119+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
120+
#else
121+
RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF;
122+
#endif /* DEVICE_USBDEVICE */
123+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 16 MHz
138124
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
139-
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
140-
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
125+
RCC_OscInitStruct.PLL.PLLM = 4; // 4 MHz
126+
RCC_OscInitStruct.PLL.PLLN = 60; // 240 MHz
141127
RCC_OscInitStruct.PLL.PLLP = 7;
142128
RCC_OscInitStruct.PLL.PLLQ = 2;
143-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
129+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz
144130

145131
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
146132
return 0; // FAIL
147133
}
148134

135+
#if DEVICE_USBDEVICE
136+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
137+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */
138+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
139+
return 0; // FAIL
140+
}
141+
#endif /* DEVICE_USBDEVICE */
142+
149143
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
150144
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
151145
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
152146
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
153147
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
154148
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
155-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
156-
return 0; // FAIL
157-
}
158-
159-
#if DEVICE_USBDEVICE
160-
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
161-
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
162-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
163-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
164-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; // 96 MHz
165-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
166-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; // 48 MHz
167-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
168-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
169-
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
170-
return 0; // FAIL
171-
}
172-
#endif /* DEVICE_USBDEVICE */
173-
174-
// Disable MSI Oscillator
175-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
176-
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
177-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
178-
HAL_RCC_OscConfig(&RCC_OscInitStruct);
179-
180-
/* Select HSI as clock source for LPUART1 */
181-
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
182-
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
183-
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
149+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
184150
return 0; // FAIL
185151
}
186152

187-
// Output clock on MCO1 pin(PA8) for debugging purpose
188-
#if DEBUG_MCO == 2
189-
if (bypass == 0) {
190-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
191-
} else {
192-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
193-
}
194-
#endif
195-
196153
return 1; // OK
197154
}
198155
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
@@ -205,72 +162,62 @@ uint8_t SetSysClock_PLL_HSI(void)
205162
{
206163
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
207164
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
208-
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
165+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
209166

210167
// Select MSI as system clock source to allow modification of the PLL configuration
211168
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
212169
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
213-
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
170+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
171+
return 0; // FAIL
172+
}
214173

215174
// Enable HSI oscillator and activate PLL with HSI as source
216-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
175+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
217176
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
218177
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
219178
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
179+
#if DEVICE_USBDEVICE
180+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
181+
#else
182+
RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF;
183+
#endif /* DEVICE_USBDEVICE */
220184
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
221185
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
222-
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
223-
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
186+
RCC_OscInitStruct.PLL.PLLM = 4; // 4 MHz
187+
RCC_OscInitStruct.PLL.PLLN = 60; // 240 MHz
224188
RCC_OscInitStruct.PLL.PLLP = 7;
225189
RCC_OscInitStruct.PLL.PLLQ = 2;
226-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
190+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz
227191
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
228192
return 0; // FAIL
229193
}
230194

195+
#if DEVICE_USBDEVICE
196+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
197+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */
198+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
199+
return 0; // FAIL
200+
}
201+
#endif /* DEVICE_USBDEVICE */
202+
231203
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
232204
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
233205
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
234206
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
235207
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
236208
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
237-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
238-
return 0; // FAIL
239-
}
240-
241-
#if DEVICE_USBDEVICE
242-
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
243-
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
244-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
245-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
246-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
247-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
248-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
249-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
250-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
251-
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
209+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
252210
return 0; // FAIL
253211
}
254-
#endif /* DEVICE_USBDEVICE */
255212

256213
// Disable MSI Oscillator
257214
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
258215
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
259216
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
260-
HAL_RCC_OscConfig(&RCC_OscInitStruct);
261-
262-
/* Select HSI as clock source for LPUART1 */
263-
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
264-
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
265-
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
217+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
266218
return 0; // FAIL
267219
}
268220

269-
// Output clock on MCO1 pin(PA8) for debugging purpose
270-
#if DEBUG_MCO == 3
271-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
272-
#endif
273-
274221
return 1; // OK
275222
}
276223
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
@@ -295,17 +242,22 @@ uint8_t SetSysClock_PLL_MSI(void)
295242

296243
HAL_RCCEx_DisableLSECSS();
297244
/* Enable MSI Oscillator and activate PLL with MSI as source */
298-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
299-
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
300-
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
301-
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
245+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
246+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
247+
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
248+
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
249+
#if DEVICE_USBDEVICE
250+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
251+
#else
252+
RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF;
253+
#endif /* DEVICE_USBDEVICE */
302254
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
303-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
255+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; /* 4 MHz */
304256
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
305257
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
306-
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
307-
RCC_OscInitStruct.PLL.PLLN = 30; /* 240 MHz */
308-
RCC_OscInitStruct.PLL.PLLP = 5; /* 48 MHz */
258+
RCC_OscInitStruct.PLL.PLLM = 1; /* 4 MHz */
259+
RCC_OscInitStruct.PLL.PLLN = 60; /* 240 MHz */
260+
RCC_OscInitStruct.PLL.PLLP = 7; /* 48 MHz */
309261
RCC_OscInitStruct.PLL.PLLQ = 2; /* 120 MHz */
310262
RCC_OscInitStruct.PLL.PLLR = 2; /* 120 MHz */
311263
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -315,10 +267,11 @@ uint8_t SetSysClock_PLL_MSI(void)
315267
HAL_RCCEx_EnableMSIPLLMode();
316268

317269
#if DEVICE_USBDEVICE
318-
/* Select MSI output as USB clock source */
319270
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
320-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
321-
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
271+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */
272+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
273+
return 0; // FAIL
274+
}
322275
#endif /* DEVICE_USBDEVICE */
323276

324277
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
@@ -327,22 +280,10 @@ uint8_t SetSysClock_PLL_MSI(void)
327280
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 120 MHz */
328281
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
329282
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
330-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
283+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
331284
return 0; // FAIL
332285
}
333286

334-
/* Select LSE as clock source for LPUART1 */
335-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
336-
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
337-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
338-
return 0; // FAIL
339-
}
340-
341-
// Output clock on MCO1 pin(PA8) for debugging purpose
342-
#if DEBUG_MCO == 4
343-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
344-
#endif
345-
346287
return 1; // OK
347288
}
348289
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/targets.json

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8454,7 +8454,7 @@
84548454
],
84558455
"config": {
84568456
"clock_source": {
8457-
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
8457+
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI | USE_PLL_MSI",
84588458
"value": "USE_PLL_MSI",
84598459
"macro_name": "CLOCK_SOURCE"
84608460
},
@@ -8467,6 +8467,7 @@
84678467
"FLASHIAP"
84688468
],
84698469
"macros_add": [
8470+
"HSE_VALUE=16000000",
84708471
"STM32L4R9xx",
84718472
"MBED_TICKLESS",
84728473
"EXTRA_IDLE_STACK_REQUIRED"

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