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LPC MCUXpresso: Add QSPI support
Signed-off-by: Mahesh Mahadevan <[email protected]>
1 parent fffb375 commit 4bbf002

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4 files changed

+358
-1
lines changed

4 files changed

+358
-1
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/PeripheralPins.h

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Original file line numberDiff line numberDiff line change
@@ -50,4 +50,11 @@ extern const PinMap PinMap_SPI_SSEL[];
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/************PWM***************/
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extern const PinMap PinMap_PWM[];
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#if DEVICE_QSPI
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/************QSPI***************/
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extern const PinMap PinMap_QSPI_DATA[];
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extern const PinMap PinMap_QSPI_SCLK[];
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extern const PinMap PinMap_QSPI_SSEL[];
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#endif
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#endif

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h

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@@ -20,6 +20,7 @@
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#include "PortNames.h"
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#include "PeripheralNames.h"
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#include "PinNames.h"
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#include <stddef.h>
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#ifdef __cplusplus
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extern "C" {
@@ -70,6 +71,12 @@ struct trng_s {
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};
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#endif
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#if DEVICE_QSPI
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struct qspi_s {
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uint32_t instance;
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};
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#endif
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#include "gpio_object.h"
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#ifdef __cplusplus

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/qspi_api.c

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@@ -0,0 +1,342 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018, ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if DEVICE_QSPI
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#include "qspi_api.h"
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#include "mbed_error.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PeripheralPins.h"
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#include "qspi_device.h"
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/* Command table indices */
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#define COMMAND_READ_INDEX (0)
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#define COMMAND_WRITE_INDEX (1)
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#define LUT1_SEQ_INDEX 0 // Pre-defined read sequence
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#define LUT2_SEQ_INDEX 4 // Pre-defined write sequence
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#define LUT3_SEQ_INDEX 8 // User-define sequence
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/* Minimum write size */
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#define MIN_SIZE 16 // At least four words of data must be written into the TX Buffer
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/* Array of QSPI peripheral base address. */
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static SPIFI_Type *const qspi_addrs[] = SPIFI_BASE_PTRS;
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extern uint32_t qspi_get_freq(void);
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qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
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{
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spifi_config_t config = {0};
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uint32_t qspiio0name = pinmap_peripheral(io0, PinMap_QSPI_DATA);
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uint32_t qspiio1name = pinmap_peripheral(io1, PinMap_QSPI_DATA);
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uint32_t qspiio2name = pinmap_peripheral(io2, PinMap_QSPI_DATA);
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uint32_t qspiio3name = pinmap_peripheral(io3, PinMap_QSPI_DATA);
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uint32_t qspiclkname = pinmap_peripheral(sclk, PinMap_QSPI_SCLK);
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uint32_t qspisselname = pinmap_peripheral(ssel, PinMap_QSPI_SSEL);
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uint32_t qspi_data_first = pinmap_merge(qspiio0name, qspiio1name);
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uint32_t qspi_data_second = pinmap_merge(qspiio2name, qspiio3name);
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uint32_t qspi_data_third = pinmap_merge(qspiclkname, qspisselname);
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if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
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qspi_data_first != qspi_data_third) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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if (qspi_frequency(obj, hz) != QSPI_STATUS_OK) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Initialize SPIFI */
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SPIFI_GetDefaultConfig(&config);
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SPIFI_Init(SPIFI0, &config);
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// tested all combinations, take first
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obj->instance = qspi_data_first;
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pinmap_pinout(io0, PinMap_QSPI_DATA);
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pinmap_pinout(io1, PinMap_QSPI_DATA);
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pinmap_pinout(io2, PinMap_QSPI_DATA);
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pinmap_pinout(io3, PinMap_QSPI_DATA);
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pinmap_pinout(sclk, PinMap_QSPI_SCLK);
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pinmap_pinout(ssel, PinMap_QSPI_SSEL);
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_free(qspi_t *obj)
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{
86+
SPIFI_Deinit(qspi_addrs[obj->instance]);
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_frequency(qspi_t *obj, int hz)
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{
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qspi_status_t status = QSPI_STATUS_OK;
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int div = qspi_get_freq() / hz;
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if ((qspi_get_freq() % hz) != 0) {
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/* Incase the exact requested baud rate can be derived then set right div,
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* else set baudrate to the closest lower value
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*/
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div++;
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}
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if (div > 256 || div < 1) {
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status = QSPI_STATUS_INVALID_PARAMETER;
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return status;
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}
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/* Set the clock divider */
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CLOCK_SetClkDiv(kCLOCK_DivSpifiClk, div, false);
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return status;
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}
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static void qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
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{
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spifi_command_t spifi_command = {0};
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SPIFI_Type *base = qspi_addrs[obj->instance];
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bool use_memory_command = false;
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/* Set the opcode & poll mode */
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spifi_command.opcode = command->instruction.value;
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spifi_command.isPollMode = false;
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/* Check if this is a data transmit */
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if (tx_data != NULL && tx_size) {
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spifi_command.dataLen = tx_size;
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spifi_command.direction = kSPIFI_DataOutput;
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}
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/* Check if this is a data receive */
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if (rx_data != NULL && rx_size) {
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spifi_command.dataLen = rx_size;
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spifi_command.direction = kSPIFI_DataInput;
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}
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/* Check if we need to set dual bit */
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if ((command->instruction.bus_width == QSPI_CFG_BUS_DUAL) ||
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(command->address.bus_width == QSPI_CFG_BUS_DUAL) ||
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(command->data.bus_width == QSPI_CFG_BUS_DUAL)) {
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base->CTRL |= SPIFI_CTRL_DUAL_MASK;
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} else {
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base->CTRL &= ~SPIFI_CTRL_DUAL_MASK;
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}
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if (command->address.disabled == true) {
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/* No flash address specified */
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spifi_command.type = kSPIFI_CommandOpcodeOnly;
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spifi_command.format = kSPIFI_CommandAllSerial;
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if ((command->instruction.bus_width == QSPI_CFG_BUS_DUAL) ||
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(command->instruction.bus_width == QSPI_CFG_BUS_QUAD)) {
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spifi_command.format = kSPIFI_CommandAllQuad;
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}
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} else {
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/* Set the address size */
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spifi_command.type = (spifi_command_type_t)(command->address.size + 2);
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/* Default to 1-1-1 mode */
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spifi_command.format = kSPIFI_CommandAllSerial;
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/* Check if it is 2-2-2 or 4-4-4 mode */
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if (((command->instruction.bus_width == QSPI_CFG_BUS_DUAL) &&
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(command->address.bus_width == QSPI_CFG_BUS_DUAL) &&
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(command->data.bus_width == QSPI_CFG_BUS_DUAL)) ||
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((command->instruction.bus_width == QSPI_CFG_BUS_QUAD) &&
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(command->address.bus_width == QSPI_CFG_BUS_QUAD) &&
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(command->data.bus_width == QSPI_CFG_BUS_QUAD))) {
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/* All quad/dual. All fields of the command are in quad/dual format. */
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spifi_command.format = kSPIFI_CommandAllQuad;
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}
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/* Check if it is 1-2-2 or 1-4-4 mode */
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if (((command->instruction.bus_width == QSPI_CFG_BUS_SINGLE) &&
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(command->address.bus_width == QSPI_CFG_BUS_DUAL) &&
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(command->data.bus_width == QSPI_CFG_BUS_DUAL)) ||
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((command->instruction.bus_width == QSPI_CFG_BUS_SINGLE) &&
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(command->address.bus_width == QSPI_CFG_BUS_QUAD) &&
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(command->data.bus_width == QSPI_CFG_BUS_QUAD))) {
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/* Serial opcode. Opcode field is serial. Other fields are quad/dual. */
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spifi_command.format = kSPIFI_CommandOpcodeSerial;
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}
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/* Check if it is 1-1-2 or 1-1-4 mode */
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if (((command->instruction.bus_width == QSPI_CFG_BUS_SINGLE) &&
184+
(command->address.bus_width == QSPI_CFG_BUS_SINGLE) &&
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(command->data.bus_width == QSPI_CFG_BUS_DUAL)) ||
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((command->instruction.bus_width == QSPI_CFG_BUS_SINGLE) &&
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(command->address.bus_width == QSPI_CFG_BUS_SINGLE) &&
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(command->data.bus_width == QSPI_CFG_BUS_QUAD))) {
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/* Quad/dual data. Data field is quad/dual, other fields are serial. */
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spifi_command.format = kSPIFI_CommandDataQuad;
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}
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/* Check if this is a data receive */
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if (rx_data != NULL && rx_size) {
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uint32_t cycles_per_byte = 8;
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if ((command->address.bus_width == QSPI_CFG_BUS_DUAL) &&
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(command->data.bus_width == QSPI_CFG_BUS_DUAL)) {
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cycles_per_byte = 4;
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}
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if ((command->address.bus_width == QSPI_CFG_BUS_QUAD) &&
202+
(command->data.bus_width == QSPI_CFG_BUS_QUAD)) {
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cycles_per_byte = 2;
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}
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/* Set dummy bytes */
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spifi_command.intermediateBytes = command->dummy_count / cycles_per_byte;
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use_memory_command = true;
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}
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/* Set the flash address */
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SPIFI_SetCommandAddress(base, command->address.value);
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}
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if (use_memory_command) {
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/* Setup command */
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SPIFI_SetMemoryCommand(base, &spifi_command);
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} else {
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/* Setup memory command */
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SPIFI_SetCommand(base, &spifi_command);
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}
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}
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qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
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{
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uint32_t to_write = *length;
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uint32_t *data_send = (uint32_t *)data;
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SPIFI_Type *base = qspi_addrs[obj->instance];
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uint32_t i = 0;
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/* Enforce word-sized access */
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if ((to_write & 0x3) != 0) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Use a pre-defined command is no write instruction is provided */
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if (command->instruction.disabled) {
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/* Set the flash address */
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SPIFI_SetCommandAddress(base, command->address.value);
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/* If no instruction provided then use the pre-defined read sequence */
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preset_spifi_command[COMMAND_WRITE_INDEX].dataLen = to_write;
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SPIFI_SetCommand(base, &preset_spifi_command[COMMAND_WRITE_INDEX]);
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} else {
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/* Prepare the write command */
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qspi_prepare_command(obj, command, data, to_write, NULL, 0);
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}
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/* Write the data */
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for (i = 0; i < to_write; i += 4, data_send++) {
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SPIFI_WriteData(base, *data_send);
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}
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/* Wait for deasseration of CS */
256+
while (SPIFI_GetStatusFlag(base) & kSPIFI_CommandWriteFinished) {
257+
}
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
263+
{
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uint32_t dest_addr = FSL_FEATURE_SPIFI_START_ADDR + command->address.value;
265+
uint32_t to_read = *length;
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SPIFI_Type *base = qspi_addrs[obj->instance];
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/* Enforce word-sized access */
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if ((to_read & 0x3) != 0) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Use a pre-defined command is no read instruction is provided */
274+
if (command->instruction.disabled) {
275+
/* If no instruction provided then use the pre-defined read sequence */
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preset_spifi_command[COMMAND_READ_INDEX].dataLen = to_read;
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SPIFI_SetMemoryCommand(base, &preset_spifi_command[COMMAND_READ_INDEX]);
278+
} else {
279+
/* Prepare for read command */
280+
qspi_prepare_command(obj, command, NULL, 0, data, to_read);
281+
}
282+
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for (uint32_t i = 0; i < to_read / 4; i++) {
284+
((uint32_t*)data)[i] = *((uint32_t *)(dest_addr) + i);
285+
}
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return QSPI_STATUS_OK;
288+
}
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qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
291+
{
292+
SPIFI_Type *base = qspi_addrs[obj->instance];
293+
294+
if (tx_size > MIN_SIZE || rx_size > MIN_SIZE) {
295+
return QSPI_STATUS_INVALID_PARAMETER;
296+
}
297+
298+
if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) {
299+
/* Setup the command */
300+
qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
301+
} else {
302+
if (tx_data != NULL && tx_size) {
303+
/* Transmit data to QSPI */
304+
uint8_t val[MIN_SIZE];
305+
306+
memset(val, 0, sizeof(val));
307+
memcpy(val, tx_data, tx_size);
308+
309+
/* Setup the command */
310+
qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
311+
312+
for (uint32_t i = 0; i < tx_size; i++) {
313+
SPIFI_WriteDataByte(base, val[i]);
314+
}
315+
}
316+
317+
if (rx_data != NULL && rx_size) {
318+
/* Receive data from QSPI */
319+
uint8_t val[MIN_SIZE];
320+
321+
memset(val, 0, sizeof(val));
322+
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/* Setup the command */
324+
qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
325+
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for (uint32_t i = 0; i < rx_size; i++) {
327+
val[i] = SPIFI_ReadDataByte(base);
328+
}
329+
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memcpy(rx_data, val, rx_size);
331+
}
332+
}
333+
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/* Wait for deasseration of CS */
335+
while (SPIFI_GetStatusFlag(base) & kSPIFI_CommandWriteFinished) {
336+
}
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return QSPI_STATUS_OK;
339+
}
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#endif
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‎targets/targets.json

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Original file line numberDiff line numberDiff line change
@@ -1839,7 +1839,8 @@
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"SPISLAVE",
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"STDIO_MESSAGES",
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"FLASH",
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"TRNG"
1842+
"TRNG",
1843+
"QSPI"
18431844
],
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"device_name": "LPC54628J512ET180",
18451846
"post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },

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