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micromint
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-126
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4 files changed

+89
-126
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‎targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1061,7 +1061,7 @@ typedef enum CGU_BASE_CLK {
10611061
CLK_BASE_APB3, /* Base clock for APB3 group */
10621062
CLK_BASE_LCD, /* Base clock for LCD pixel clock */
10631063
#if defined(CHIP_LPC43XX)
1064-
CLK_BASE_ADCHS, /* Base clock for ADCHS */
1064+
CLK_BASE_VADC, /* Base clock for VADC */
10651065
#else
10661066
CLK_BASE_RESERVED3,
10671067
#endif

‎targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.c

Lines changed: 82 additions & 113 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@
3333
#include "LPC43xx.h"
3434

3535
#define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
36-
#define PLL1_MSEL (MAX_CLOCK_FREQ / CRYSTAL_MAIN_FREQ_IN)
3736

3837
/* Clock variables */
3938
#if (CLOCK_SETUP)
@@ -49,34 +48,31 @@ typedef struct {
4948
uint16_t mode; /* SCU pin mode and function */
5049
} PINMUX_GRP_T;
5150

52-
#if (SPIFI_INIT)
53-
/* SCU configuration for SPIFI pins */
54-
static const PINMUX_GRP_T spifi_pinmux[] = {
51+
/* Pins to initialize before clocks are configured */
52+
static const PINMUX_GRP_T pre_clock_mux[] = {
5553
/* SPIFI pins */
56-
{SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
57-
{SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
58-
{SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
59-
{SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
60-
{SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
61-
{SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
54+
{SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
55+
{SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
56+
{SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
57+
{SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
58+
{SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
59+
{SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
6260
};
63-
#endif
6461

65-
/* SCU configuration for board pins */
66-
static const PINMUX_GRP_T board_pinmux[] = {
62+
/* Pins to initialize after clocks are configured */
63+
static const PINMUX_GRP_T post_clock_mux[] = {
6764
/* Boot pins */
68-
{SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
69-
{SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
70-
{SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
71-
{SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
65+
{SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
66+
{SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
67+
{SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
68+
{SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
7269
/* Micromint Bambino 200/210 */
7370
{SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
74-
{SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
75-
{SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
71+
{SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
72+
{SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
7673
/* Micromint Bambino 210 */
77-
{SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
78-
{SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
79-
{SCU_REG(0xF, 4), (SCU_PINIO_FAST | 0x0)}, /* PF_4 SSP1_CLK */
74+
{SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
75+
{SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
8076
};
8177

8278
#if (CLOCK_SETUP)
@@ -87,47 +83,42 @@ struct CLK_BASE_STATES {
8783
uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
8884
};
8985

90-
/* Base clocks - sources and states (mostly ON) */
86+
/* Initial base clock states are mostly on */
9187
static const struct CLK_BASE_STATES clock_states[] = {
92-
{CLK_BASE_SAFE, CLKIN_IRC, 0},
93-
{CLK_BASE_APB1, CLKIN_MAINPLL, 0},
94-
{CLK_BASE_APB3, CLKIN_MAINPLL, 0},
95-
{CLK_BASE_USB0, CLKIN_USBPLL, 1},
96-
#if defined(CHIP_LPC43XX)
88+
{CLK_BASE_SAFE, CLKIN_IRC, 0},
89+
{CLK_BASE_APB1, CLKIN_MAINPLL, 0},
90+
{CLK_BASE_APB3, CLKIN_MAINPLL, 0},
91+
{CLK_BASE_USB0, CLKIN_USBPLL, 1},
9792
{CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
98-
{CLK_BASE_SPI, CLKIN_MAINPLL, 0},
99-
{CLK_BASE_ADCHS, CLKIN_MAINPLL, 1},
100-
#endif
101-
{CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
102-
{CLK_BASE_SSP0, CLKIN_MAINPLL, 0},
103-
{CLK_BASE_SSP1, CLKIN_MAINPLL, 0},
104-
{CLK_BASE_UART0, CLKIN_MAINPLL, 0},
105-
{CLK_BASE_UART1, CLKIN_MAINPLL, 0},
106-
{CLK_BASE_UART2, CLKIN_MAINPLL, 0},
107-
{CLK_BASE_UART3, CLKIN_MAINPLL, 0},
108-
{CLK_BASE_OUT, CLKINPUT_PD, 0},
109-
{CLK_BASE_APLL, CLKINPUT_PD, 0},
110-
{CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
111-
{CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
112-
113-
/* Ethernet clocks */
93+
{CLK_BASE_SPI, CLKIN_MAINPLL, 0},
11494
{CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
11595
#if defined(USE_RMII)
11696
{CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
11797
#else
11898
{CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
11999
#endif
100+
{CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
101+
{CLK_BASE_SSP0, CLKIN_IDIVC, 0},
102+
{CLK_BASE_SSP1, CLKIN_IDIVC, 0},
103+
{CLK_BASE_UART0, CLKIN_MAINPLL, 0},
104+
{CLK_BASE_UART1, CLKIN_MAINPLL, 0},
105+
{CLK_BASE_UART2, CLKIN_MAINPLL, 0},
106+
{CLK_BASE_UART3, CLKIN_MAINPLL, 0},
107+
{CLK_BASE_OUT, CLKINPUT_PD, 0},
108+
{CLK_BASE_APLL, CLKINPUT_PD, 0},
109+
{CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
110+
{CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
120111

121112
/* Clocks derived from dividers */
122-
{CLK_BASE_LCD, CLKIN_IDIVC, 0},
123-
{CLK_BASE_USB1, CLKIN_IDIVD, 1}
113+
{CLK_BASE_LCD, CLKIN_IDIVC, 0},
114+
{CLK_BASE_USB1, CLKIN_IDIVD, 1}
124115
};
125116
#endif /* defined(CLOCK_SETUP) */
126117

127118
/* Local functions */
128119
static uint32_t SystemGetMainPLLHz(void);
129-
static void SystemSetupPins(void);
130120
static void SystemSetupClock(void);
121+
static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
131122
static void SystemSetupMemory(void);
132123
static void WaitUs(uint32_t us);
133124

@@ -164,8 +155,9 @@ void SystemInit(void)
164155
fpuInit();
165156
#endif
166157

167-
SystemSetupPins(); /* Configure MCU pins */
158+
SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
168159
SystemSetupClock(); /* Configure processor and peripheral clocks */
160+
SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
169161
SystemSetupMemory(); /* Configure external memory */
170162
#endif /* !defined(CORE_M0) */
171163

@@ -222,37 +214,6 @@ uint32_t SystemGetMainPLLHz(void)
222214
}
223215

224216
#if !defined(CORE_M0)
225-
/*
226-
* SystemSetupPins() - Configure MCU pins
227-
*/
228-
void SystemSetupPins(void)
229-
{
230-
#if (PIN_SETUP)
231-
uint32_t i;
232-
233-
/* Reset peripherals */
234-
LPC_RGU->RESET_CTRL0 = 0x105F0000;
235-
LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
236-
237-
/* Configure board pins */
238-
for (i = 0; i < COUNT_OF(board_pinmux); i++) {
239-
*(board_pinmux[i].reg) = board_pinmux[i].mode;
240-
}
241-
242-
/* Configure dedicated clock pins */
243-
for (i = 0; i < 3; i++) {
244-
LPC_SCU->SFSCLK[i] = SCU_PINIO_FAST;
245-
}
246-
247-
#if (SPIFI_INIT)
248-
/* Configure SPIFI pins */
249-
for (i = 0; i < COUNT_OF(spifi_pinmux); i++) {
250-
*(spifi_pinmux[i].reg) = spifi_pinmux[i].mode;
251-
}
252-
#endif
253-
#endif /* PIN_SETUP */
254-
}
255-
256217
/*
257218
* SystemSetupClock() - Set processor and peripheral clocks
258219
*
@@ -272,51 +233,44 @@ void SystemSetupClock(void)
272233
#if (CLOCK_SETUP)
273234
uint32_t i;
274235

275-
#if (FLASH_INIT)
276-
/* Setup flash acceleration for MCUs with internal flash */
277-
i = MAX_CLOCK_FREQ / 21510000;
278-
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (i << 12);
279-
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (i << 12);
280-
#endif
236+
/* Switch main clock to Internal RC (IRC) while setting up PLL1 */
237+
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
238+
/* Set prescaler/divider on SSP1 assuming 204 MHz clock */
239+
LPC_SSP1->CR1 &= ~(1 << 1);
240+
LPC_SSP1->CPSR = 0x0002;
241+
LPC_SSP1->CR0 = 0x00006507;
242+
LPC_SSP1->CR1 |= (1 << 1);
281243

282-
/* Clear bypass, enable crystal oscillator and wait 100 us */
283-
LPC_CGU->XTAL_OSC_CTRL &= (~2);
284-
LPC_CGU->XTAL_OSC_CTRL &= (~1);
244+
/* Enable the oscillator and wait 100 us */
245+
LPC_CGU->XTAL_OSC_CTRL = 0;
285246
WaitUs(100);
286247

287-
/* Switch main clock to crystal while setting up PLL1 */
288-
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_CRYSTAL << 24);
289-
290-
/* Configure PLL1 (MAINPLL) for main clock */
291-
/* Change PLL1 to 108 Mhz (psel=1, nsel=1, msel=9 for 12 MHz*9=108 MHz) */
292-
LPC_CGU->PLL1_CTRL = (1 << 6) | (0 << 7) | (0 << 8) | (1 << 11) | (0 << 12)
293-
| (8 << 16) | (CLKIN_CRYSTAL << 24);
294-
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
295-
WaitUs(50);
296-
297-
/* Connect main clock to PLL1 */
298-
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
299-
300-
/* Change PLL1 to MAX_CLOCK_FREQ */
301-
/* PLL1_MSEL=17 for 12 MHz*17=204 MHz, PLL1_MSEL=15 for 12 MHz*15=180 MHz */
302-
LPC_CGU->PLL1_CTRL = (1 << 6) | (1 << 7) |(0 << 8) | (1 << 11) | (0 << 12)
303-
| ((PLL1_MSEL - 1) << 16) | (CLKIN_CRYSTAL << 24);
304-
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
305-
306-
/* Reset and enable 32Khz oscillator */
307-
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
308-
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
309-
310248
#if (SPIFI_INIT)
311249
/* Setup SPIFI control register and no-opcode mode */
312250
LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
313251
LPC_SPIFI->IDATA = 0xA5;
314-
315252
/* Switch IDIVE clock to IRC and connect to SPIFI clock */
316253
LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
317254
LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
318255
#endif /* SPIFI_INIT */
319256

257+
/* Configure PLL1 (MAINPLL) for main clock */
258+
LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
259+
260+
/* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
261+
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
262+
| (CLKIN_MAINPLL << 24);
263+
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
264+
WaitUs(100);
265+
266+
/* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
267+
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
268+
| (CLKIN_MAINPLL << 24);
269+
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
270+
271+
/* Connect main clock to PLL1 */
272+
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
273+
320274
/* Set USB PLL dividers for 480 MHz (for USB0) */
321275
LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
322276
LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
@@ -340,6 +294,21 @@ void SystemSetupClock(void)
340294
| (1 << 11) | (clock_states[i].clkin << 24);
341295
}
342296
#endif /* CLOCK_SETUP */
297+
/* Reset peripherals */
298+
LPC_RGU->RESET_CTRL0 = 0x105F0000;
299+
LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
300+
}
301+
302+
/*
303+
* SystemSetupPins() - Configure MCU pins
304+
*/
305+
void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
306+
{
307+
uint32_t i;
308+
309+
for (i = 0; i < n; i++) {
310+
*(mux[i].reg) = mux[i].mode;
311+
}
343312
}
344313

345314
/*
@@ -348,7 +317,7 @@ void SystemSetupClock(void)
348317
void SystemSetupMemory(void)
349318
{
350319
#if (MEMORY_SETUP)
351-
/* Todo: EMC setup for boards with external memory */
320+
/* None required for boards without external memory */
352321
#endif /* MEMORY_SETUP */
353322
}
354323

‎targets/TARGET_NXP/TARGET_LPC43XX/device/system_LPC43xx.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,6 @@ extern "C" {
3838
#define CLOCK_SETUP 1 /* Configure clocks during initialization */
3939
#define MEMORY_SETUP 0 /* Configure external memory during init */
4040
#define SPIFI_INIT 1 /* Initialize SPIFI */
41-
#define FLASH_INIT 0 /* Initialize internal flash */
4241

4342
/* Crystal frequency into device */
4443
#define CRYSTAL_MAIN_FREQ_IN 12000000

‎targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,7 @@
2929

3030
// configuration options
3131
#define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
32-
#ifndef PWM_MODE
33-
#define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
34-
#endif
32+
#define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
3533

3634
// macros
3735
#define PWM_SETCOUNT(x) (x - 1) // set count value
@@ -165,8 +163,8 @@ static void _pwmout_dev_init() {
165163

166164
// initialize SCT outputs
167165
for (i = 0; i < CONFIG_SCT_nOU; i++) {
168-
LPC_SCT->OUT[i].SET = 0; // defer set event until pulsewidth defined
169-
LPC_SCT->OUT[i].CLR = (1 << 0); // event 0 clears PWM pin
166+
LPC_SCT->OUT[i].SET = (1 << 0); // event 0 will set SCTOUT_xx
167+
LPC_SCT->OUT[i].CLR = 0; // set clear event when duty cycle
170168
}
171169
LPC_SCT->OUTPUT = 0; // default outputs to clear
172170

@@ -254,18 +252,15 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
254252
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
255253
// calculate number of ticks
256254
uint32_t v = pwm_clock_mhz * us;
257-
uint32_t i = obj->pwm;
258255
//MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
259256

260257
if (v > 0) {
261258
// set new match register value and enable SCT output
262259
*PWM_MR(obj->mr) = PWM_SETCOUNT(v);
263-
LPC_SCT->OUT[i].SET = (1 << 0); // event 0 sets PWM pin
264-
LPC_SCT->OUT[i].CLR = (1 << obj->mr); // match event clears PWM pin
260+
LPC_SCT->OUT[obj->pwm].CLR = (1 << obj->mr); // on event will clear PWM_XX
265261
} else {
266-
// set match to zero and clear SCT output
262+
// set match to zero and disable SCT output
267263
*PWM_MR(obj->mr) = 0;
268-
LPC_SCT->OUT[i].SET = 0; // no set event if no pulsewidth defined
269-
LPC_SCT->OUT[i].CLR = (1 << 0); // event 0 clears PWM pin
264+
LPC_SCT->OUT[obj->pwm].CLR = 0;
270265
}
271266
}

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