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[NUC472] Fix PWM1 clock source setting error
1 parent 005f032 commit 4ec0751

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+60
-41
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2 files changed

+60
-41
lines changed

‎targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c

Lines changed: 31 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file PWM.c
33
* @version V1.00
4-
* $Revision: 22 $
5-
* $Date: 14/10/02 9:21a $
4+
* $Revision: 26 $
5+
* $Date: 15/11/18 2:34p $
66
* @brief NUC472/NUC442 PWM driver source file
77
*
88
* @note
@@ -52,14 +52,14 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
5252
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
5353
* existing frequency of other channel.
5454
*/
55-
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
56-
uint32_t u32ChannelNum,
57-
uint32_t u32Frequency,
58-
uint32_t u32DutyCycle,
59-
uint32_t u32Frequency2)
55+
uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
56+
uint32_t u32ChannelNum,
57+
uint32_t u32Frequency,
58+
uint32_t u32DutyCycle,
59+
uint32_t u32Frequency2)
6060
{
6161
uint32_t i;
62-
uint32_t u32PWM_CLock;
62+
uint32_t u32PWM_CLock = __HIRC;
6363
uint8_t u8Divider = 1, u8Prescale = 0xFF;
6464
uint16_t u16CNR = 0xFFFF;
6565

@@ -100,15 +100,15 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
100100
}
101101
} else if (pwm == PWM1) {
102102
if (u32ChannelNum < 2) {
103-
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
103+
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
104104
u32PWM_CLock = __HXT;
105-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
105+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
106106
u32PWM_CLock = __LXT;
107-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
107+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
108108
u32PWM_CLock = SystemCoreClock;
109-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
109+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
110110
u32PWM_CLock = __HIRC;
111-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
111+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
112112
u32PWM_CLock = __LIRC;
113113
} else if (u32ChannelNum < 4) {
114114
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@@ -207,7 +207,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
207207
uint32_t u32CaptureEdge)
208208
{
209209
uint32_t i;
210-
uint32_t u32PWM_CLock;
210+
uint32_t u32PWM_CLock = __HIRC;
211211
uint8_t u8Divider = 1, u8Prescale = 0xFF;
212212
uint16_t u16CNR = 0xFFFF;
213213

@@ -248,15 +248,15 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
248248
}
249249
} else if (pwm == PWM1) {
250250
if (u32ChannelNum < 2) {
251-
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
251+
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
252252
u32PWM_CLock = __HXT;
253-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
253+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
254254
u32PWM_CLock = __LXT;
255-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
255+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
256256
u32PWM_CLock = SystemCoreClock;
257-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
257+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
258258
u32PWM_CLock = __HIRC;
259-
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
259+
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
260260
u32PWM_CLock = __LIRC;
261261
} else if (u32ChannelNum < 4) {
262262
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@@ -451,6 +451,7 @@ uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
451451
* - \ref PWM_BRK0_CPO0
452452
* - \ref PWM_BRK0_CPO1
453453
* - \ref PWM_BRK0_CPO2
454+
* - \ref PWM_BRK1_LVDBK
454455
* - \ref PWM_BK1SEL_BKP1
455456
* - \ref PWM_BK1SEL_CPO0
456457
* - \ref PWM_BK1SEL_CPO1
@@ -463,20 +464,29 @@ void PWM_EnableFaultBrake (PWM_T *pwm,
463464
{
464465
if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
465466
pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
467+
else if (u32BrakeSource == PWM_BRK1_LVDBK)
468+
pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
466469
else
467470
pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
471+
472+
pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
473+
468474
}
469475

470476
/**
471477
* @brief This function clear fault brake flag
472478
* @param[in] pwm The base address of PWM module
473-
* @param[in] u32BrakeSource This parameter is not used
479+
* @param[in] u32BrakeSource Fault brake source 0 or 1
480+
* 0: brake 0, 1: brake 1
474481
* @return None
475482
* @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
476483
*/
477484
void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
478485
{
479-
pwm->INTSTS = PWM_INTSTS_BRKLK0_Msk;
486+
if (u32BrakeSource == 0)
487+
pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
488+
else
489+
pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
480490
}
481491

482492
/**

‎targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h

Lines changed: 29 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file pwm.h
33
* @version V1.00
4-
* $Revision: 19 $
5-
* $Date: 14/10/06 1:36p $
4+
* $Revision: 22 $
5+
* $Date: 15/11/16 2:08p $
66
* @brief NUC472/NUC442 PWM driver header file
77
*
88
* @note
@@ -29,14 +29,18 @@ extern "C"
2929
@{
3030
*/
3131
#define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
32+
#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
33+
#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
34+
#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
35+
#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
36+
#define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */
37+
#define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */
3238
#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
3339
#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
3440
#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
3541
#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
3642
#define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
3743
#define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
38-
#define PWM_CH_6_MASK (64UL) /*!< PWM channel 6 mask \hideinitializer */
39-
#define PWM_CH_7_MASK (128UL) /*!< PWM channel 7 mask \hideinitializer */
4044
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
4145
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
4246
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
@@ -48,10 +52,11 @@ extern "C"
4852
#define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
4953
#define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
5054
#define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
51-
#define PWM_BRK0_BKP0 (0UL) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
55+
#define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
5256
#define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
5357
#define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
5458
#define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
59+
#define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */
5560
#define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
5661
#define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
5762
#define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
@@ -79,47 +84,47 @@ extern "C"
7984
* @return None
8085
* \hideinitializer
8186
*/
82-
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_OUTMODE_Msk)
87+
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
8388

8489
/**
8590
* @brief This macro disable complementary mode, and enable independent mode.
8691
* @param[in] pwm The base address of PWM module
8792
* @return None
8893
* \hideinitializer
8994
*/
90-
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_OUTMODE_Msk)
95+
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
9196

9297
/**
9398
* @brief This macro enable group mode
9499
* @param[in] pwm The base address of PWM module
95100
* @return None
96101
* \hideinitializer
97102
*/
98-
#define PWM_ENABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_GROUPEN_Msk)
103+
#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
99104

100105
/**
101106
* @brief This macro disable group mode
102107
* @param[in] pwm The base address of PWM module
103108
* @return None
104109
* \hideinitializer
105110
*/
106-
#define PWM_DISABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_GROUPEN_Msk)
111+
#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
107112

108113
/**
109114
* @brief This macro enable synchronous mode
110115
* @param[in] pwm The base address of PWM module
111116
* @return None
112117
* \hideinitializer
113118
*/
114-
#define PWM_ENABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_SYNCEN_Msk)
119+
#define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
115120

116121
/**
117122
* @brief This macro disable synchronous mode, and enable independent mode.
118123
* @param[in] pwm The base address of PWM module
119124
* @return None
120125
* \hideinitializer
121126
*/
122-
#define PWM_DISABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_SYNCEN_Msk)
127+
#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
123128

124129
/**
125130
* @brief This macro enable output inverter of specified channel(s)
@@ -129,7 +134,7 @@ extern "C"
129134
* @return None
130135
* \hideinitializer
131136
*/
132-
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) (pwm->CTL |= (u32ChannelMask << PWM_CTL_PINV_Pos)
137+
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
133138

134139
/**
135140
* @brief This macro get captured rising data
@@ -138,7 +143,7 @@ extern "C"
138143
* @return None
139144
* \hideinitializer
140145
*/
141-
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->RCAPDAT0 + 2 * u32ChannelNum))
146+
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
142147

143148
/**
144149
* @brief This macro get captured falling data
@@ -147,7 +152,7 @@ extern "C"
147152
* @return None
148153
* \hideinitializer
149154
*/
150-
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->FCAPDAT0 + 2 * u32ChannelNum))
155+
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
151156

152157
/**
153158
* @brief This macro mask output output logic to high or low
@@ -158,7 +163,7 @@ extern "C"
158163
* @return None
159164
* \hideinitializer
160165
*/
161-
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) (pwm->MSKEN |= u32ChannelMask)
166+
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
162167

163168
/**
164169
* @brief This macro set the prescaler of the selected channel
@@ -171,7 +176,7 @@ extern "C"
171176
* \hideinitializer
172177
*/
173178
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
174-
(pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
179+
(pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
175180

176181
/**
177182
* @brief This macro set the divider of the selected channel
@@ -187,7 +192,7 @@ extern "C"
187192
* \hideinitializer
188193
*/
189194
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
190-
(pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
195+
((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
191196

192197
/**
193198
* @brief This macro set the duty of the selected channel
@@ -198,7 +203,7 @@ extern "C"
198203
* @note This new setting will take effect on next PWM period
199204
* \hideinitializer
200205
*/
201-
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (pwm->CMPDAT[u32ChannelNum] = (u32CMR))
206+
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
202207

203208
/**
204209
* @brief This macro set the period of the selected channel
@@ -210,7 +215,7 @@ extern "C"
210215
* @note PWM counter will stop if period length set to 0
211216
* \hideinitializer
212217
*/
213-
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (pwm->PERIOD[u32ChannelNum] = (u32CNR))
218+
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
214219

215220
/**
216221
* @brief This macro set the PWM aligned type
@@ -224,7 +229,11 @@ extern "C"
224229
* \hideinitializer
225230
*/
226231
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
227-
(pwm->CTL = (pwm->CTL & ~(u32ChannelMask << PWM_CTL_CNTMODE_Pos) | (u32AlignedType << PWM_CTL_CNTMODE_Pos))
232+
do { \
233+
(pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
234+
if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
235+
(pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
236+
} while(0)
228237

229238

230239
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,

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