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Add one board Green Tea SPI Communication Test
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‎TESTS/mbed_hal/spi_com/README.md

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One Board SPI Communication Test
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=============
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### tests-mbed_hal-spi_com
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Overview
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----------------
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This is the SPI communication test which verifies various SPI configuration variants. The test is based on Green Tea framework. The test transfers data between SPI master and SPI slave on the same device.
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Test Setup
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----------------
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1. **Pre-requirements**
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- One Mbed board with SPI support
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- Board must have two SPI peripherals available
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- Board must support SPI slave mode
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- Wire connection between SPI interfaces
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![alt text](spi_ob_wire_connection.png)
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2. **Running the test**
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- Test assumes that SPI pins are defined in target's `PinNames.h` file:
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- `SPI0_MOSI`, `SPI0_MISO`, `SPI0_SCK`, `SPI0_CS`
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- `SPI1_MOSI`, `SPI1_MISO`, `SPI1_SCK`, `SPI1_CS`
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- Wire the 4 pins for each peripheral.
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- Set `MANUAL_TEST` macro in the test to `1`.
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- Run the test using the following command:
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`mbed test -t TOOLCHAIN -m BOARD -n tests-mbed_hal-spi_com`
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Test scenario
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----------------
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Typical SPI transmission schema during the test is shown below:
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![alt text](com_test.png)
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Five predefined(different) symbols are sent in both directions using different SPI configurations.
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- Test for synchronous API
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- CS is asserted high (inactive state).
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- Configuration is validated against device capabilities.
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- If master or slave cannot handle this configuration the test case is skipped.
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- Format configuration is set for both master and slave.
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- Frequency configuration is set on the master peripheral.
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- Reception buffers and semaphores are reinitialized.
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- A thread is started for the slave side.
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- A thread is started for the master side.
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- The master thread asserts CS to 0 (active state), performs the transfer and asserts CS back to 1.
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- The test thread (main) waits until either the semaphore is given twice or we it reaches a timeout.
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- Master & slave rx buffers are respectively compared to slave & master tx buffers.
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- If a buffer do not match, then the test fails.
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- Both SPI peripheral are freed and the next test starts.
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**Note:**
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On master side data is transferred symbol by symbol (i.e. when 5 symbols is to be transferred, then transfer routine is called 5 times in loop). This is the limitation of the one board SPI communication test.
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- Test for asynchronous API
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- CS is asserted high (inactive state).
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- Configuration is validated against device capabilities
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- If master or slave cannot handle this configuration the test case is skipped.
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- Format configuration is set for both master and slave.
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- Frequency configuration is set on the master peripheral.
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- Reception buffers and semaphores are reinitialized.
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- The spi_transfer_async() function is called for the slave peripheral.
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- The CS is asserted to 0 (active state).
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- spi_trasnfer_async() is called for the master peripheral.
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- The CS is asserted back to 1 (inactive state).
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- Master & slave rx buffers are respectively compared to slave & master tx buffers.
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- If a buffer do not match, then the test fails.
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- Both SPI peripheral are freed and the next test starts.
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What is verified by the test?
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----------------
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| | Test case | Testing | Description |
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|-----|----------------------------------------------------------------|---------------------------|----------------------------------------------------------|
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| 1 | **SPI master-slave sync com - default config** | Sync/General | Verifies most commonly used SPI configuration* |
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| 2 | SPI master-slave sync com - symbol size: 1 | Sync/Symbol sizes | Symbol size is equal to 1 |
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| 3 | SPI master-slave sync com - symbol size: 7 | Sync/Symbol sizes | Symbol size is equal to 7 |
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| 4 | SPI master-slave sync com - symbol size: 9 | Sync/Symbol sizes | Symbol size is equal to 9 |
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| 5 | SPI master-slave sync com - symbol size: 15 | Sync/Symbol sizes | Symbol size is equal to 15 |
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| 6 | SPI master-slave sync com - symbol size: 16 | Sync/Symbol sizes | Symbol size is equal to 16 |
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| 7 | SPI master-slave sync com - symbol size: 17 | Sync/Symbol sizes | Symbol size is equal to 17 |
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| 8 | SPI master-slave sync com - symbol size: 31 | Sync/Symbol sizes | Symbol size is equal to 31 |
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| 9 | SPI master-slave sync com - symbol size: 32 | Sync/Symbol sizes | Symbol size is equal to 32 |
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| 10 | SPI master-slave sync com - mode: idle low, sample second edge | Sync/Clock polarity/phase | Clock idle high/sampling on the first edge |
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| 11 | SPI master-slave sync com - mode: idle high, sample first edge | Sync/Clock polarity/phase | Clock idle high/sampling on the second edge |
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| 12 | SPI master-slave sync com - mode: idle high, sample second edge| Sync/Clock polarity/phase | Clock idle low/sampling on the first edge |
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| 13 | SPI master-slave sync com - bit ordering: LSB first | Sync/Bit order | LSB transmitted first |
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| 14 | SPI master-slave sync com - master: manual ss | Sync/SS handling | Internal SS handling by master |
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| 15 | SPI master-slave sync com - freq testing: 200 KHz | Sync/Frequency | Minimum required frequency (200 kHz) |
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| 16 | SPI master-slave sync com - freq testing: 2 MHz | Sync/Frequency | Maximum required frequency (2 MHz) |
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| 17 | SPI master-slave sync com - freq testing: min defined | Sync/Frequency | Minimum frequency specified in capabilities |
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| 18 | SPI master-slave sync com - freq testing: max defined | Sync/Frequency | Maximum frequency specified in capabilities |
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| 19 | SPI master-slave sync com - master: TX undefined | Sync/Buffers | Master TX buffer is undefined (NULL) |
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| 20 | SPI master-slave sync com - master: RX undefined | Sync/Buffers | Master RX buffer is undefined (NULL) |
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| 21 | SPI master-slave sync com - slave: TX undefined | Sync/Buffers | Slave TX buffer is undefined (NULL) |
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| 22 | SPI master-slave sync com - slave: RX undefined | Sync/Buffers | Slave RX buffer is undefined (NULL) |
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| 23 | SPI master-slave sync com - master: TX > RX | Sync/Buffers | Master TX buffer size is greater than RX buffer size |
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| 24 | SPI master-slave sync com - master: TX < RX | Sync/Buffers | Master TX buffer size is less than RX buffer size |
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| 25 | SPI master-slave sync com - slave: TX > RX | Sync/Buffers | SLAVE TX buffer size is greater than RX buffer size |
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| 26 | SPI master-slave sync com - slave: TX < RX | Sync/Buffers | SLAVE TX buffer size is less than RX buffer size |
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| 27 | SPI master-slave sync com - one symbol | Sync/Buffers | 1 symbol is transmitted |
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| 28 | SPI master-slave sync com - long buffer | Sync/Buffers | 64 symbols are transmitted |
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| 29 | SPI master-slave async com - default config | Aync/General | Verifies most commonly used SPI configuration |
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| 30 | SPI master-slave sync com - symbol size: 1 | Aync/Symbol sizes | Symbol size is equal to 1 |
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| 31 | SPI master-slave sync com - symbol size: 7 | Aync/Symbol sizes | Symbol size is equal to 7 |
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| 32 | SPI master-slave sync com - symbol size: 9 | Aync/Symbol sizes | Symbol size is equal to 9 |
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| 33 | SPI master-slave sync com - symbol size: 15 | Aync/Symbol sizes | Symbol size is equal to 15 |
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| 34 | SPI master-slave sync com - symbol size: 16 | Aync/Symbol sizes | Symbol size is equal to 16 |
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| 35 | SPI master-slave sync com - symbol size: 17 | Aync/Symbol sizes | Symbol size is equal to 17 |
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| 36 | SPI master-slave sync com - symbol size: 31 | Aync/Symbol sizes | Symbol size is equal to 31 |
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| 37 | SPI master-slave sync com - symbol size: 32 | Aync/Symbol sizes | Symbol size is equal to 32 |
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| 38 | SPI master-slave sync com - mode: idle low, sample second edge | Aync/Clock polarity/phase | Clock idle high/sampling on the first edge |
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| 39 | SPI master-slave sync com - mode: idle high, sample first edge | Aync/Clock polarity/phase | Clock idle high/sampling on the second edge |
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| 40 | SPI master-slave sync com - mode: idle high, sample second edge| Aync/Clock polarity/phase | Clock idle low/sampling on the first edge |
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| 41 | SPI master-slave sync com - bit ordering: LSB first | Aync/Bit order | LSB transmitted first |
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| 42 | SPI master-slave sync com - freq testing: 200 KHz | Aync/Frequency | Minimum required frequency (200 kHz) |
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| 43 | SPI master-slave sync com - freq testing: 2 MHz | Aync/Frequency | Maximum required frequency (2 MHz) |
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| 44 | SPI master-slave sync com - master: manual ss | Aync/SS handling | Internal SS handling by master |
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| 45 | SPI master-slave sync com - one symbol | Aync/Buffers | 1 symbol is transmitted |
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| 46 | SPI master-slave sync com - long buffer | Aync/Buffers | 32 symbols are transmitted |
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Synchronous and asynchronous modes are tested separately.
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`*` - `default config` test case verifies the most typical SPI configuration which is:
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- Symbol size: 8 bits
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- Clock polarity/phase: Clock idle low/sampling on the first edge
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- Bit order: MSB first
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- SS handling: external (manual)
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- Duplex: Full duplex
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- Frequency: 1 MHz
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- Synchronous mode (blocking)
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- RX, TX buffers defined
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- RX buffer length is equal to TX buffer length (5 symbols are transmitted in both directions)
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Other test cases differs from the `default config` always only by one setting (e.g. `symbol size: 16` test case has the same scenario, but 16 bit symbols are transmitted).
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Test Limitations
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----------------
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Synchronous mode:
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- Test uses two threads in to handle master-slave data transfer, because of that master is sending symbols one by one (when five symbols are to be sent, then spi_transfer() function is called five times and in each call one symbol is transferred). This will allow slave thread to read transmitted symbols.
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- Half-Duplex mode cannot be tested.
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Asynchronous mode:
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**Note:**
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In async mode cases when rx buffer size is different than tx buffer size and half-duplex mode are not supported.
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- Undefined RX/TX buffers(NULL) cannot be tested.
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- High frequencies cannot be tested.
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It is recommended to use Ice Tea version of the SPI communication test which do not have such limitations and is more reliable.
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Expected result
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----------------
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The test exits without errors.

‎TESTS/mbed_hal/spi_com/com_test.png

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