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Merge pull request #17 from matthewelse/forpullrequest
LPC1114 Port Pull Request
2 parents 4302720 + 7827d62 commit 5489309

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‎.gitignore

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.mr.developer.cfg
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.project
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.pydevproject
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output.txt
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uVision Project/
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# Sublime Text Project Files
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*.sublime*
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*.bak
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debug.log

‎README.md

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@@ -28,6 +28,7 @@ NXP:
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* LPC4088 (Cortex-M4)
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* LPC4330 (Cortex-M4 + Cortex-M0)
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* LPC1347 (Cortex-M3)
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* LPC1114 (Cortex-M0)
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Freescale:
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* [KL25Z](http://mbed.org/handbook/mbed-FRDM-KL25Z) (Cortex-M0+)

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h

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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/LPC1114.sct

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LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
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ER_IROM1 0x00000000 0x8000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0xF40
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RW_IRAM1 0x100000C0 0xF40 {
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.ANY (+RW +ZI)
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}
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}
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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s

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;/*****************************************************************************
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; * @file: startup_LPC11xx.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
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; * for the NXP LPC11xx Device Series
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; * @version: V1.0
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; * @date: 25. Nov. 2008
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2008 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
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DCD FLEX_INT1_IRQHandler ;
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DCD FLEX_INT2_IRQHandler ;
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DCD FLEX_INT3_IRQHandler ;
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DCD FLEX_INT4_IRQHandler ;
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DCD FLEX_INT5_IRQHandler ;
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DCD FLEX_INT6_IRQHandler ;
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DCD FLEX_INT7_IRQHandler ;
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DCD GINT0_IRQHandler ;
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DCD GINT1_IRQHandler ; PIO0 (0:7)
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ;
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DCD Reserved_IRQHandler ;
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DCD Reserved_IRQHandler ;
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
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DCD TIMER32_0_IRQHandler ; 32-bit Timer0
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
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DCD WDT_IRQHandler ; Watchdog timer
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
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; for particular peripheral.
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;NMI_Handler PROC
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; EXPORT NMI_Handler [WEAK]
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; B .
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; ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Reserved_IRQHandler PROC
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EXPORT Reserved_IRQHandler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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; for LPC11Uxx (With USB)
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EXPORT NMI_Handler [WEAK]
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EXPORT FLEX_INT0_IRQHandler [WEAK]
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EXPORT FLEX_INT1_IRQHandler [WEAK]
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EXPORT FLEX_INT2_IRQHandler [WEAK]
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EXPORT FLEX_INT3_IRQHandler [WEAK]
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EXPORT FLEX_INT4_IRQHandler [WEAK]
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EXPORT FLEX_INT5_IRQHandler [WEAK]
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EXPORT FLEX_INT6_IRQHandler [WEAK]
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EXPORT FLEX_INT7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT TIMER16_0_IRQHandler [WEAK]
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EXPORT TIMER16_1_IRQHandler [WEAK]
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EXPORT TIMER32_0_IRQHandler [WEAK]
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EXPORT TIMER32_1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT UART_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT USB_FIQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT USBWakeup_IRQHandler [WEAK]
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NMI_Handler
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FLEX_INT0_IRQHandler
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FLEX_INT1_IRQHandler
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FLEX_INT2_IRQHandler
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FLEX_INT3_IRQHandler
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FLEX_INT4_IRQHandler
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FLEX_INT5_IRQHandler
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FLEX_INT6_IRQHandler
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FLEX_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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SSP1_IRQHandler
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I2C_IRQHandler
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TIMER16_0_IRQHandler
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TIMER16_1_IRQHandler
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TIMER32_0_IRQHandler
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TIMER32_1_IRQHandler
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SSP0_IRQHandler
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UART_IRQHandler
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USB_IRQHandler
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USB_FIQHandler
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ADC_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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FMC_IRQHandler
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USBWakeup_IRQHandler
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B .
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ENDP
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ALIGN
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END

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/sys.cpp

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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/LPC1114.sct

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LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
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ER_IROM1 0x00000000 0x8000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0xF40
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RW_IRAM1 0x100000C0 0xF40 {
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.ANY (+RW +ZI)
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}
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}
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