Skip to content

Commit 55f9b01

Browse files
screamerbgscreamerbg
committed
Add GHI_MBUINO target support
1 parent 8d5d92f commit 55f9b01

File tree

9 files changed

+1173
-0
lines changed

9 files changed

+1173
-0
lines changed

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_GHI_MBUINO/LPC11U24.sct

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
2+
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
3+
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
4+
*.o (RESET, +First)
5+
*(InRoot$$Sections)
6+
.ANY (+RO)
7+
}
8+
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
9+
; 8KB - 0xC0 = 0x1F40
10+
RW_IRAM1 0x100000C0 0x1F40 {
11+
.ANY (+RW +ZI)
12+
}
13+
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
14+
.ANY (USBRAM)
15+
}
16+
}
17+

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_GHI_MBUINO/startup_LPC11xx.s

Lines changed: 325 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,325 @@
1+
;/*****************************************************************************
2+
; * @file: startup_LPC11xx.s
3+
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
4+
; * for the NXP LPC11xx Device Series
5+
; * @version: V1.0
6+
; * @date: 25. Nov. 2008
7+
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
8+
; *
9+
; * Copyright (C) 2008 ARM Limited. All rights reserved.
10+
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
11+
; * processor based microcontrollers. This file can be freely distributed
12+
; * within development tools that are supporting such ARM based processors.
13+
; *
14+
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15+
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16+
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17+
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18+
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
19+
; *
20+
; *****************************************************************************/
21+
22+
Stack_Size EQU 0x00000400
23+
24+
AREA STACK, NOINIT, READWRITE, ALIGN=3
25+
EXPORT __initial_sp
26+
27+
Stack_Mem SPACE Stack_Size
28+
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
29+
30+
31+
Heap_Size EQU 0x00000000
32+
33+
AREA HEAP, NOINIT, READWRITE, ALIGN=3
34+
EXPORT __heap_base
35+
EXPORT __heap_limit
36+
37+
__heap_base
38+
Heap_Mem SPACE Heap_Size
39+
__heap_limit
40+
41+
PRESERVE8
42+
THUMB
43+
44+
; Vector Table Mapped to Address 0 at Reset
45+
46+
AREA RESET, DATA, READONLY
47+
EXPORT __Vectors
48+
49+
__Vectors DCD __initial_sp ; Top of Stack
50+
DCD Reset_Handler ; Reset Handler
51+
DCD NMI_Handler ; NMI Handler
52+
DCD HardFault_Handler ; Hard Fault Handler
53+
DCD MemManage_Handler ; MPU Fault Handler
54+
DCD BusFault_Handler ; Bus Fault Handler
55+
DCD UsageFault_Handler ; Usage Fault Handler
56+
DCD 0 ; Reserved
57+
DCD 0 ; Reserved
58+
DCD 0 ; Reserved
59+
DCD 0 ; Reserved
60+
DCD SVC_Handler ; SVCall Handler
61+
DCD DebugMon_Handler ; Debug Monitor Handler
62+
DCD 0 ; Reserved
63+
DCD PendSV_Handler ; PendSV Handler
64+
DCD SysTick_Handler ; SysTick Handler
65+
66+
; External Interrupts
67+
; for LPC11Uxx (With USB)
68+
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
69+
DCD FLEX_INT1_IRQHandler
70+
DCD FLEX_INT2_IRQHandler
71+
DCD FLEX_INT3_IRQHandler
72+
DCD FLEX_INT4_IRQHandler
73+
DCD FLEX_INT5_IRQHandler
74+
DCD FLEX_INT6_IRQHandler
75+
DCD FLEX_INT7_IRQHandler
76+
DCD GINT0_IRQHandler
77+
DCD GINT1_IRQHandler ; PIO0 (0:7)
78+
DCD Reserved_IRQHandler ; Reserved
79+
DCD Reserved_IRQHandler
80+
DCD Reserved_IRQHandler
81+
DCD Reserved_IRQHandler
82+
DCD SSP1_IRQHandler ; SSP1
83+
DCD I2C_IRQHandler ; I2C
84+
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
85+
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
86+
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
87+
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
88+
DCD SSP0_IRQHandler ; SSP0
89+
DCD UART_IRQHandler ; UART
90+
DCD USB_IRQHandler ; USB IRQ
91+
DCD USB_FIQHandler ; USB FIQ
92+
DCD ADC_IRQHandler ; A/D Converter
93+
DCD WDT_IRQHandler ; Watchdog timer
94+
DCD BOD_IRQHandler ; Brown Out Detect
95+
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
96+
DCD Reserved_IRQHandler ; Reserved
97+
DCD Reserved_IRQHandler ; Reserved
98+
DCD USBWakeup_IRQHandler ; USB wake up
99+
DCD Reserved_IRQHandler ; Reserved
100+
101+
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
102+
103+
DCD 0xFFFFFFFF ; Datafill
104+
DCD 0xFFFFFFFF ; Datafill
105+
DCD 0xFFFFFFFF ; Datafill
106+
DCD 0xFFFFFFFF ; Datafill
107+
DCD 0xFFFFFFFF ; Datafill
108+
DCD 0xFFFFFFFF ; Datafill
109+
DCD 0xFFFFFFFF ; Datafill
110+
DCD 0xFFFFFFFF ; Datafill
111+
DCD 0xFFFFFFFF ; Datafill
112+
DCD 0xFFFFFFFF ; Datafill
113+
114+
DCD 0xFFFFFFFF ; Datafill
115+
DCD 0xFFFFFFFF ; Datafill
116+
DCD 0xFFFFFFFF ; Datafill
117+
DCD 0xFFFFFFFF ; Datafill
118+
DCD 0xFFFFFFFF ; Datafill
119+
DCD 0xFFFFFFFF ; Datafill
120+
DCD 0xFFFFFFFF ; Datafill
121+
DCD 0xFFFFFFFF ; Datafill
122+
DCD 0xFFFFFFFF ; Datafill
123+
DCD 0xFFFFFFFF ; Datafill
124+
125+
DCD 0xFFFFFFFF ; Datafill
126+
DCD 0xFFFFFFFF ; Datafill
127+
DCD 0xFFFFFFFF ; Datafill
128+
DCD 0xFFFFFFFF ; Datafill
129+
DCD 0xFFFFFFFF ; Datafill
130+
DCD 0xFFFFFFFF ; Datafill
131+
DCD 0xFFFFFFFF ; Datafill
132+
DCD 0xFFFFFFFF ; Datafill
133+
DCD 0xFFFFFFFF ; Datafill
134+
DCD 0xFFFFFFFF ; Datafill
135+
136+
DCD 0xFFFFFFFF ; Datafill
137+
DCD 0xFFFFFFFF ; Datafill
138+
DCD 0xFFFFFFFF ; Datafill
139+
DCD 0xFFFFFFFF ; Datafill
140+
DCD 0xFFFFFFFF ; Datafill
141+
DCD 0xFFFFFFFF ; Datafill
142+
DCD 0xFFFFFFFF ; Datafill
143+
DCD 0xFFFFFFFF ; Datafill
144+
DCD 0xFFFFFFFF ; Datafill
145+
DCD 0xFFFFFFFF ; Datafill
146+
147+
DCD 0xFFFFFFFF ; Datafill
148+
DCD 0xFFFFFFFF ; Datafill
149+
DCD 0xFFFFFFFF ; Datafill
150+
DCD 0xFFFFFFFF ; Datafill
151+
DCD 0xFFFFFFFF ; Datafill
152+
DCD 0xFFFFFFFF ; Datafill
153+
DCD 0xFFFFFFFF ; Datafill
154+
DCD 0xFFFFFFFF ; Datafill
155+
DCD 0xFFFFFFFF ; Datafill
156+
DCD 0xFFFFFFFF ; Datafill
157+
158+
DCD 0xFFFFFFFF ; Datafill
159+
DCD 0xFFFFFFFF ; Datafill
160+
DCD 0xFFFFFFFF ; Datafill
161+
DCD 0xFFFFFFFF ; Datafill
162+
DCD 0xFFFFFFFF ; Datafill
163+
DCD 0xFFFFFFFF ; Datafill
164+
DCD 0xFFFFFFFF ; Datafill
165+
DCD 0xFFFFFFFF ; Datafill
166+
DCD 0xFFFFFFFF ; Datafill
167+
DCD 0xFFFFFFFF ; Datafill
168+
169+
DCD 0xFFFFFFFF ; Datafill
170+
DCD 0xFFFFFFFF ; Datafill
171+
DCD 0xFFFFFFFF ; Datafill
172+
DCD 0xFFFFFFFF ; Datafill
173+
DCD 0xFFFFFFFF ; Datafill
174+
DCD 0xFFFFFFFF ; Datafill
175+
DCD 0xFFFFFFFF ; Datafill
176+
DCD 0xFFFFFFFF ; Datafill
177+
DCD 0xFFFFFFFF ; Datafill
178+
DCD 0xFFFFFFFF ; Datafill
179+
180+
DCD 0xFFFFFFFF ; Datafill
181+
DCD 0xFFFFFFFF ; Datafill
182+
DCD 0xFFFFFFFF ; Datafill
183+
DCD 0xFFFFFFFF ; Datafill
184+
DCD 0xFFFFFFFF ; Datafill
185+
DCD 0xFFFFFFFF ; Datafill
186+
DCD 0xFFFFFFFF ; Datafill
187+
DCD 0xFFFFFFFF ; Datafill
188+
DCD 0xFFFFFFFF ; Datafill
189+
DCD 0xFFFFFFFF ; Datafill
190+
191+
IF :LNOT::DEF:NO_CRP
192+
AREA |.ARM.__at_0x02FC|, CODE, READONLY
193+
CRP_Key DCD 0xFFFFFFFF
194+
ENDIF
195+
196+
197+
AREA |.text|, CODE, READONLY
198+
199+
200+
201+
; Reset Handler
202+
203+
Reset_Handler PROC
204+
EXPORT Reset_Handler [WEAK]
205+
IMPORT SystemInit
206+
IMPORT __main
207+
LDR R0, =SystemInit
208+
BLX R0
209+
LDR R0, =__main
210+
BX R0
211+
ENDP
212+
213+
; Dummy Exception Handlers (infinite loops which can be modified)
214+
215+
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
216+
; for particular peripheral.
217+
;NMI_Handler PROC
218+
; EXPORT NMI_Handler [WEAK]
219+
; B .
220+
; ENDP
221+
HardFault_Handler\
222+
PROC
223+
EXPORT HardFault_Handler [WEAK]
224+
B .
225+
ENDP
226+
MemManage_Handler\
227+
PROC
228+
EXPORT MemManage_Handler [WEAK]
229+
B .
230+
ENDP
231+
BusFault_Handler\
232+
PROC
233+
EXPORT BusFault_Handler [WEAK]
234+
B .
235+
ENDP
236+
UsageFault_Handler\
237+
PROC
238+
EXPORT UsageFault_Handler [WEAK]
239+
B .
240+
ENDP
241+
SVC_Handler PROC
242+
EXPORT SVC_Handler [WEAK]
243+
B .
244+
ENDP
245+
DebugMon_Handler\
246+
PROC
247+
EXPORT DebugMon_Handler [WEAK]
248+
B .
249+
ENDP
250+
PendSV_Handler PROC
251+
EXPORT PendSV_Handler [WEAK]
252+
B .
253+
ENDP
254+
SysTick_Handler PROC
255+
EXPORT SysTick_Handler [WEAK]
256+
B .
257+
ENDP
258+
Reserved_IRQHandler PROC
259+
EXPORT Reserved_IRQHandler [WEAK]
260+
B .
261+
ENDP
262+
263+
Default_Handler PROC
264+
; for LPC11Uxx (With USB)
265+
EXPORT NMI_Handler [WEAK]
266+
EXPORT FLEX_INT0_IRQHandler [WEAK]
267+
EXPORT FLEX_INT1_IRQHandler [WEAK]
268+
EXPORT FLEX_INT2_IRQHandler [WEAK]
269+
EXPORT FLEX_INT3_IRQHandler [WEAK]
270+
EXPORT FLEX_INT4_IRQHandler [WEAK]
271+
EXPORT FLEX_INT5_IRQHandler [WEAK]
272+
EXPORT FLEX_INT6_IRQHandler [WEAK]
273+
EXPORT FLEX_INT7_IRQHandler [WEAK]
274+
EXPORT GINT0_IRQHandler [WEAK]
275+
EXPORT GINT1_IRQHandler [WEAK]
276+
EXPORT SSP1_IRQHandler [WEAK]
277+
EXPORT I2C_IRQHandler [WEAK]
278+
EXPORT TIMER16_0_IRQHandler [WEAK]
279+
EXPORT TIMER16_1_IRQHandler [WEAK]
280+
EXPORT TIMER32_0_IRQHandler [WEAK]
281+
EXPORT TIMER32_1_IRQHandler [WEAK]
282+
EXPORT SSP0_IRQHandler [WEAK]
283+
EXPORT UART_IRQHandler [WEAK]
284+
285+
EXPORT USB_IRQHandler [WEAK]
286+
EXPORT USB_FIQHandler [WEAK]
287+
EXPORT ADC_IRQHandler [WEAK]
288+
EXPORT WDT_IRQHandler [WEAK]
289+
EXPORT BOD_IRQHandler [WEAK]
290+
EXPORT FMC_IRQHandler [WEAK]
291+
EXPORT USBWakeup_IRQHandler [WEAK]
292+
293+
NMI_Handler
294+
FLEX_INT0_IRQHandler
295+
FLEX_INT1_IRQHandler
296+
FLEX_INT2_IRQHandler
297+
FLEX_INT3_IRQHandler
298+
FLEX_INT4_IRQHandler
299+
FLEX_INT5_IRQHandler
300+
FLEX_INT6_IRQHandler
301+
FLEX_INT7_IRQHandler
302+
GINT0_IRQHandler
303+
GINT1_IRQHandler
304+
SSP1_IRQHandler
305+
I2C_IRQHandler
306+
TIMER16_0_IRQHandler
307+
TIMER16_1_IRQHandler
308+
TIMER32_0_IRQHandler
309+
TIMER32_1_IRQHandler
310+
SSP0_IRQHandler
311+
UART_IRQHandler
312+
USB_IRQHandler
313+
USB_FIQHandler
314+
ADC_IRQHandler
315+
WDT_IRQHandler
316+
BOD_IRQHandler
317+
FMC_IRQHandler
318+
USBWakeup_IRQHandler
319+
320+
B .
321+
322+
ENDP
323+
324+
ALIGN
325+
END

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_GHI_MBUINO/LPC11U24.sct

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
2+
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
3+
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
4+
*.o (RESET, +First)
5+
*(InRoot$$Sections)
6+
.ANY (+RO)
7+
}
8+
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
9+
; 8KB - 0xC0 = 0x1F40
10+
RW_IRAM1 0x100000C0 0x1F40 {
11+
.ANY (+RW +ZI)
12+
}
13+
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
14+
.ANY (USBRAM)
15+
}
16+
}
17+

0 commit comments

Comments
 (0)