Core(A): Updated __FPU_Enable function (VFP register count detection)

Author: RobertRostohar

cmsis/TARGET_CORTEX_A/cmsis_armcc.h

@@ -134,13 +134,15 @@
 
 /**
   \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #define __REV                             __rev
 
 /**
   \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
@@ -153,12 +155,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
 #endif
 
 /**
-  \brief   Reverse byte order in signed short value
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 {
   revsh r0, r0
   bx lr
@@ -351,14 +354,16 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
 /** \brief  Get Mode
     \return                Processor Mode
  */
-__STATIC_INLINE uint32_t __get_mode(void) {
+__STATIC_INLINE uint32_t __get_mode(void)
+{
   return (__get_CPSR() & 0x1FU);
 }
 
 /** \brief  Set Mode
     \param [in]    mode  Mode value to set
  */
-__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
   MOV  r1, lr
   MSR  CPSR_C, r0
   BX   r1
@@ -443,15 +448,30 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
  * Include common core functions to access Coprocessor 15 registers
  */
 
-#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); Rt = tmp; } while(0)
-#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = Rt; } while(0)
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+  do { \
+    uint32_t ltmp, htmp; \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+  } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+  do { \
+    const uint64_t tmp = (Rt); \
+    const uint32_t ltmp = (uint32_t)(tmp); \
+    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+  } while(0)
 
 #include "cmsis_cp15.h"
 
 /** \brief  Clean and Invalidate the entire data or unified cache
  * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
  */
-__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
+__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
+{
         ARM
 
         PUSH    {R4-R11}
@@ -510,7 +530,8 @@ Finished
 
   Critical section, called from undef handler, so systick is disabled
  */
-__STATIC_INLINE __ASM void __FPU_Enable(void) {
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
         ARM
 
         //Permit access to VFP/NEON, registers by modifying CPACR
@@ -528,7 +549,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) {
 
         //Initialise VFP/NEON registers to 0
         MOV     R2,#0
-  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
+
         //Initialise D16 registers to 0
         VMOV    D0, R2,R2
         VMOV    D1, R2,R2
@@ -546,7 +567,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) {
         VMOV    D13,R2,R2
         VMOV    D14,R2,R2
         VMOV    D15,R2,R2
-  ENDIF
+
   IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
         //Initialise D32 registers to 0
         VMOV    D16,R2,R2

cmsis/TARGET_CORTEX_A/cmsis_armclang.h

@@ -25,6 +25,8 @@
 #ifndef __CMSIS_ARMCLANG_H
 #define __CMSIS_ARMCLANG_H
 
+#pragma clang system_header   /* treat file as system include file */
+
 #ifndef __ARM_COMPAT_H
 #include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
 #endif
@@ -148,38 +150,29 @@
 
 /**
   \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#define __REV                             __builtin_bswap32
+#define __REV(value)   __builtin_bswap32(value)
 
 /**
   \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
-  return result;
-}
-#endif
+#define __REV16(value) __ROR(__REV(value), 16)
+
 
 /**
-  \brief   Reverse byte order in signed short value
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  int32_t result;
-  __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
-  return result;
-}
-#endif
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
 
 /**
   \brief   Rotate Right in unsigned value (32 bit)
@@ -188,31 +181,37 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t
   \param [in]    op2  Number of Bits to rotate
   \return               Rotated value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
   return (op1 >> op2) | (op1 << (32U - op2));
 }
 
+
 /**
   \brief   Breakpoint
   \param [in]    value  is ignored by the processor.
                  If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+#define __BKPT(value)   __ASM volatile ("bkpt "#value)
 
 /**
   \brief   Reverse bit order of value
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#define __RBIT                            __builtin_arm_rbit
+#define __RBIT          __builtin_arm_rbit
 
 /**
   \brief   Count leading zeros
   \param [in]  value  Value to count the leading zeros
   \return             number of leading zeros in value
  */
-#define __CLZ                             __builtin_clz
+#define __CLZ           (uint8_t)__builtin_clz
 
 /**
   \brief   LDR Exclusive (8 bit)
@@ -313,7 +312,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
 /** \brief  Get CPSR Register
     \return               CPSR Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void)
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
 {
   uint32_t result;
   __ASM volatile("MRS %0, cpsr" : "=r" (result) );
@@ -323,31 +322,31 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void)
 /** \brief  Set CPSR Register
     \param [in]    cpsr  CPSR value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
 {
 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
 }
 
 /** \brief  Get Mode
     \return                Processor Mode
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void)
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
 {
 	return (__get_CPSR() & 0x1FU);
 }
 
 /** \brief  Set Mode
     \param [in]    mode  Mode value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode)
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
 {
   __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
 }
 
 /** \brief  Get Stack Pointer
     \return Stack Pointer value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP()
+__STATIC_FORCEINLINE uint32_t __get_SP()
 {
   uint32_t result;
   __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
@@ -357,15 +356,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP()
 /** \brief  Set Stack Pointer
     \param [in]    stack  Stack Pointer value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack)
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
 {
   __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
 }
 
 /** \brief  Get USR/SYS Stack Pointer
     \return USR/SYS Stack Pointer value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr()
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
 {
   uint32_t cpsr;
   uint32_t result;
@@ -382,7 +381,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr()
 /** \brief  Set USR/SYS Stack Pointer
     \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack)
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
 {
   uint32_t cpsr;
   __ASM volatile(
@@ -397,7 +396,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfP
 /** \brief  Get FPEXC
     \return               Floating Point Exception Control register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void)
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
 {
 #if (__FPU_PRESENT == 1)
   uint32_t result;
@@ -411,7 +410,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void)
 /** \brief  Set FPEXC
     \param [in]    fpexc  Floating Point Exception Control value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
 {
 #if (__FPU_PRESENT == 1)
   __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
@@ -424,6 +423,8 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
 
 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
 
 #include "cmsis_cp15.h"
 
@@ -494,24 +495,23 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
 __STATIC_INLINE void __FPU_Enable(void)
 {
   __ASM volatile(
-	    //Permit access to VFP/NEON, registers by modifying CPACR
+    //Permit access to VFP/NEON, registers by modifying CPACR
     "        MRC     p15,0,R1,c1,c0,2  \n"
     "        ORR     R1,R1,#0x00F00000 \n"
     "        MCR     p15,0,R1,c1,c0,2  \n"
 
-	    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
     "        ISB                       \n"
 
-	    //Enable VFP/NEON
+    //Enable VFP/NEON
     "        VMRS    R1,FPEXC          \n"
     "        ORR     R1,R1,#0x40000000 \n"
     "        VMSR    FPEXC,R1          \n"
 
-	    //Initialise VFP/NEON registers to 0
+    //Initialise VFP/NEON registers to 0
     "        MOV     R2,#0             \n"
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
-	    //Initialise D16 registers to 0
+    //Initialise D16 registers to 0
     "        VMOV    D0, R2,R2         \n"
     "        VMOV    D1, R2,R2         \n"
     "        VMOV    D2, R2,R2         \n"
@@ -528,10 +528,9 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D13,R2,R2         \n"
     "        VMOV    D14,R2,R2         \n"
     "        VMOV    D15,R2,R2         \n"
-#endif
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-	    //Initialise D32 registers to 0
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"
     "        VMOV    D18,R2,R2         \n"
@@ -548,9 +547,9 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D29,R2,R2         \n"
     "        VMOV    D30,R2,R2         \n"
     "        VMOV    D31,R2,R2         \n"
-    ".endif                            \n"
 #endif
-	    //Initialise FPSCR to a known state
+
+    //Initialise FPSCR to a known state
     "        VMRS    R2,FPSCR          \n"
     "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
     "        AND     R2,R2,R3          \n"