Skip to content

Commit 575f9f9

Browse files
committed
[NUCLEO_F302R8] Fix issue with SystemCoreClock variable update.
This variable must be placed outside the RAM initialization section.
1 parent c675516 commit 575f9f9

File tree

3 files changed

+15
-11
lines changed

3 files changed

+15
-11
lines changed

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
3737
}
3838

3939
; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
40-
RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
40+
; + 4 more bytes reserved for the SystemCoreClock variable
41+
RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
4142
.ANY (+RW +ZI)
4243
}
4344

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f302x8.sct

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@ LR_IROM1 0x08000000 0x10000 { ; load region size_region
3737
}
3838

3939
; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
40-
RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data
40+
; + 4 more bytes reserved for the SystemCoreClock variable
41+
RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4)) { ; RW data
4142
.ANY (+RW +ZI)
4243
}
4344

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,10 @@
141141
* @{
142142
*/
143143

144-
uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
144+
// [TODO] Do the same for other compilers
145+
// Warning: the RAM is initialized AFTER the SetSysClock function is called.
146+
// This variable must be placed outside the initialized section (see scatter file).
147+
uint32_t SystemCoreClock __attribute__((at(0x20000188))) = 64000000; /* Default with HSI. Will be updated if HSE is used */
145148

146149
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
147150

@@ -208,16 +211,16 @@ void SystemInit(void)
208211
/* Disable all interrupts */
209212
RCC->CIR = 0x00000000;
210213

214+
/* Configure the System clock source, PLL Multiplier and Divider factors,
215+
AHB/APBx prescalers and Flash settings */
216+
SetSysClock();
217+
211218
/* Configure the Vector Table location add offset address ------------------*/
212219
#ifdef VECT_TAB_SRAM
213220
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
214221
#else
215222
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
216223
#endif
217-
218-
/* Configure the System clock source, PLL Multiplier and Divider factors,
219-
AHB/APBx prescalers and Flash settings */
220-
SetSysClock();
221224
}
222225

223226
/**
@@ -330,9 +333,6 @@ void SetSysClock(void)
330333
}
331334
}
332335
}
333-
334-
/* Update SystemCoreClock variable */
335-
SystemCoreClockUpdate();
336336

337337
/* Output SYSCLK on MCO pin(PA8) for debugging purpose */
338338
/*
@@ -411,7 +411,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
411411
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
412412
{
413413
}
414-
414+
415+
SystemCoreClock = 72000000;
415416
return 1; // OK
416417
}
417418
else
@@ -459,6 +460,7 @@ uint8_t SetSysClock_PLL_HSI(void)
459460
{
460461
}
461462

463+
SystemCoreClock = 64000000;
462464
return 1; // OK
463465
}
464466

0 commit comments

Comments
 (0)