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LMESTMLMESTM
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Test montage QSPI volant
Test QSPI Ok avec QSPI2 + PF0/1/2/3/4 + PG12
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6 files changed

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6 files changed

+75
-1
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‎TESTS/mbed_hal/qspi/flash_configs/MX25RXX35F_config.h

Lines changed: 1 addition & 1 deletion
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@@ -82,7 +82,7 @@
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
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// max frequency for basic rw operation (for fast mode)
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#define QSPI_COMMON_MAX_FREQUENCY 32000000
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#define QSPI_COMMON_MAX_FREQUENCY 2000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 2

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

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@@ -20,6 +20,9 @@
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#if defined(TARGET_DISCO_L475VG_IOT01A)
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#include "MX25RXX35F_config.h" // MX25R6435F
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#elif defined(TARGET_NUCLEO_L4R5ZI_P)
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#include "MX25RXX35F_config.h" // MX25R6435F
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#elif defined(TARGET_DISCO_F413ZH)
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#include "N25Q128A_config.h" // N25Q128A13EF840F
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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralNames.h

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@@ -83,6 +83,11 @@ typedef enum {
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CAN_1 = (int)CAN1_BASE
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} CANName;
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typedef enum {
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QSPI_1 = (int)OCTOSPI1_R_BASE,
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QSPI_2 = (int)OCTOSPI2_R_BASE
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} QSPIName;
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralPins.c

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Original file line numberDiff line numberDiff line change
@@ -376,3 +376,46 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
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{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
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{NC, NC, 0}
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};
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//*** QUADSPI ***
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MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
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{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_BK1_IO0
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{PF_0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
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{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_BK1_IO1
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{PF_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
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{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_BK1_IO2
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{PF_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
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{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_BK1_IO3
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{PF_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
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{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_CLK
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{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_CLK
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{PF_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
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{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_NCS
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{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // QUADSPI_NCS
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{PG_12, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_OCTOSPIM_P2)}, // QUADSPI_BK1_IO0
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{NC, NC, 0}
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};
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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PinNames.h

Lines changed: 18 additions & 0 deletions
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@@ -320,6 +320,24 @@ typedef enum {
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SYS_WKUP4 = PA_2,
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SYS_WKUP5 = PC_5,
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/**** QSPI FLASH pins ****/
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/* OSPI1
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QSPI_FLASH1_IO0 = PE_12,
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QSPI_FLASH1_IO1 = PB_0,
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QSPI_FLASH1_IO2 = PE_14,
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QSPI_FLASH1_IO3 = PE_15,
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QSPI_FLASH1_SCK = PA_3,
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QSPI_FLASH1_CSN = PE_11,
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*/
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/* OSPI2 */
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QSPI_FLASH1_IO0 = PF_0,
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QSPI_FLASH1_IO1 = PF_1,
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QSPI_FLASH1_IO2 = PF_2,
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QSPI_FLASH1_IO3 = PF_3,
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QSPI_FLASH1_SCK = PF_4,
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QSPI_FLASH1_CSN = PG_12,
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// Not connected
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NC = (int)0xFFFFFFFF
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} PinName;

‎targets/targets.json

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@@ -7924,6 +7924,10 @@
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"MBED_TICKLESS",
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"EXTRA_IDLE_STACK_REQUIRED"
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],
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"components_add": [
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"QSPIF",
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"FLASHIAP"
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],
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"overrides": { "lpticker_delay_ticks": 0 },
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"detect_code": ["0776"],
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"device_has_add": [
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"SERIAL_ASYNCH",
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"TRNG",
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"FLASH",
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"QSPI",
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"MPU"
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],
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"release_versions": ["2", "5"],

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