@@ -52,8 +52,36 @@ void mbed_sdk_init(void)
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/* Set HCLK source form HXT and HCLK source divide 1 */
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CLK_SetHCLK (CLK_CLKSEL0_HCLK_S_HXT , CLK_HCLK_CLK_DIVIDER (1 ));
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- /* Set HCLK frequency 42MHz */
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- CLK_SetCoreClock (42000000 );
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+ /* Select HXT/HIRC to clock PLL
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+ *
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+ * Comparison between HXT/HIRC-clocked PLL:
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+ * 1. Spare HXT on board if only HIRC is used.
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+ * 2. HIRC has shorter stable time.
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+ * 3. HXT has better accuracy. USBD requires HXT-clocked PLL.
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+ * 4. HIRC has shorter wake-up time from power-down mode.
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+ * Per test, wake-up time from power-down mode would take:
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+ * T1. 1~13 ms (proportional to deep sleep time) with HXT-clocked PLL as HCLK clock source
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+ * T2. <1 ms with HIRC-clocked PLL as HCLK clock source
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+ * T1 will fail Greentea test which requires max 10 ms wake-up time.
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+ *
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+ * If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
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+ * it will go T1 with HXT already enabled in front. So we manually configure
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+ * it to choose HXT/HIRC-clocked PLL.
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+ */
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+ #define NU_HXT_PLL 1
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+ #define NU_HIRC_PLL 2
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+
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+ #ifndef NU_CLOCK_PLL
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+ #define NU_CLOCK_PLL NU_HIRC_PLL
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+ #endif
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+
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+ #if (NU_CLOCK_PLL == NU_HXT_PLL )
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+ CLK_EnablePLL (CLK_PLLCTL_PLL_SRC_HXT , FREQ_42MHZ * 2 );
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+ CLK_SetHCLK (CLK_CLKSEL0_HCLK_S_PLL , CLK_HCLK_CLK_DIVIDER (2 ));
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+ #elif (NU_CLOCK_PLL == NU_HIRC_PLL )
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+ CLK_EnablePLL (CLK_PLLCTL_PLL_SRC_HIRC , FREQ_42MHZ * 2 );
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+ CLK_SetHCLK (CLK_CLKSEL0_HCLK_S_PLL , CLK_HCLK_CLK_DIVIDER (2 ));
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+ #endif
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/* Update System Core Clock */
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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