MCUXpresso Kinetis SPI drive: Add a delay between CS assertion and first sclk edge

mmahadevan108 · mmahadevan108 · commit 5af80db8b65b · 2019-08-23T07:11:43.000-05:00
1. FPGA test shield requires at least half sclk period delay between
CS assertion and first sclk edge
2. Update Kinetis SPI drivers to match what is already done for K64F

Signed-off-by: Mahesh Mahadevan &lt;mahesh.mahadevan@nxp.com&gt;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c
@@ -80,7 +80,6 @@ void spi_free(spi_t *obj)
 
 void spi_format(spi_t *obj, int bits, int mode, int slave)
 {
-
     dspi_master_config_t master_config;
     dspi_slave_config_t slave_config;
 
@@ -100,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/spi_api.c
@@ -61,7 +61,6 @@ void spi_free(spi_t *obj)
 
 void spi_format(spi_t *obj, int bits, int mode, int slave)
 {
-
     dspi_master_config_t master_config;
     dspi_slave_config_t slave_config;
 
@@ -81,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
@@ -95,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
     DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
 }
 
-static inline int spi_readable(spi_t * obj)
+static inline int spi_readable(spi_t *obj)
 {
     return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/spi_api.c
@@ -80,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
@@ -94,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
     DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
 }
 
-static inline int spi_readable(spi_t * obj)
+static inline int spi_readable(spi_t *obj)
 {
     return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c
@@ -99,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c
@@ -99,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/spi_api.c
@@ -80,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
     }
@@ -94,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
     DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
 }
 
-static inline int spi_readable(spi_t * obj)
+static inline int spi_readable(spi_t *obj)
 {
     return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c
@@ -90,7 +90,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
         master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
         master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
         master_config.ctarConfig.direction = kDSPI_MsbFirst;
-        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
 
         DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance]));
     }
@@ -104,7 +104,7 @@ void spi_frequency(spi_t *obj, int hz)
     DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
 }
 
-static inline int spi_readable(spi_t * obj)
+static inline int spi_readable(spi_t *obj)
 {
     return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag);
 }
@@ -314,14 +314,14 @@ static void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void
 
 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
 {
-    if(spi_active(obj)) {
+    if (spi_active(obj)) {
         return;
     }
 
     /* check corner case */
-    if(tx_length == 0) {
+    if (tx_length == 0) {
         tx_length = rx_length;
-        tx = (void*) 0;
+        tx = (void *) 0;
     }
 
     /* First, set the buffer */
@@ -422,7 +422,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
 void spi_abort_asynch(spi_t *obj)
 {
     // If we're not currently transferring, then there's nothing to do here
-    if(spi_active(obj) == 0) {
+    if (spi_active(obj) == 0) {
         return;
     }
 

Original file line number	Diff line number	Diff line change
`@@ -80,7 +80,6 @@ void spi_free(spi_t *obj)`
`80`	`80`
`81`	`81`	`void spi_format(spi_t *obj, int bits, int mode, int slave)`
`82`	`82`	`{`
`83`		`-`
`84`	`83`	`dspi_master_config_t master_config;`
`85`	`84`	`dspi_slave_config_t slave_config;`
`86`	`85`
`@@ -100,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)`
`100`	`99`	`master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;`
`101`	`100`	`master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;`
`102`	`101`	`master_config.ctarConfig.direction = kDSPI_MsbFirst;`
`103`		`- master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;`
	`102`	`+ master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;`
`104`	`103`
`105`	`104`	`DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));`
`106`	`105`	`}`
Original file line number	Diff line number	Diff line change
`@@ -61,7 +61,6 @@ void spi_free(spi_t *obj)`
`61`	`61`
`62`	`62`	`void spi_format(spi_t *obj, int bits, int mode, int slave)`
`63`	`63`	`{`
`64`		`-`
`65`	`64`	`dspi_master_config_t master_config;`
`66`	`65`	`dspi_slave_config_t slave_config;`
`67`	`66`
`@@ -81,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)`
`81`	`80`	`master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;`
`82`	`81`	`master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;`
`83`	`82`	`master_config.ctarConfig.direction = kDSPI_MsbFirst;`
`84`		`- master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;`
	`83`	`+ master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;`
`85`	`84`
`86`	`85`	`DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));`
`87`	`86`	`}`
`@@ -95,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)`
`95`	`94`	`DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);`
`96`	`95`	`}`
`97`	`96`
`98`		`-static inline int spi_readable(spi_t * obj)`
	`97`	`+static inline int spi_readable(spi_t *obj)`
`99`	`98`	`{`
`100`	`99`	`return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);`
`101`	`100`	`}`
Original file line number	Diff line number	Diff line change
`@@ -80,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)`
`80`	`80`	`master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;`
`81`	`81`	`master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;`
`82`	`82`	`master_config.ctarConfig.direction = kDSPI_MsbFirst;`
`83`		`- master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;`
	`83`	`+ master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;`
`84`	`84`
`85`	`85`	`DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));`
`86`	`86`	`}`
`@@ -94,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)`
`94`	`94`	`DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);`
`95`	`95`	`}`
`96`	`96`
`97`		`-static inline int spi_readable(spi_t * obj)`
	`97`	`+static inline int spi_readable(spi_t *obj)`
`98`	`98`	`{`
`99`	`99`	`return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);`
`100`	`100`	`}`
Original file line number	Diff line number	Diff line change
`@@ -99,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)`
`99`	`99`	`master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;`
`100`	`100`	`master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;`
`101`	`101`	`master_config.ctarConfig.direction = kDSPI_MsbFirst;`
`102`		`- master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;`
	`102`	`+ master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;`
`103`	`103`
`104`	`104`	`DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));`
`105`	`105`	`}`
Original file line number	Diff line number	Diff line change
`@@ -90,7 +90,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)`
`90`	`90`	`master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;`
`91`	`91`	`master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;`
`92`	`92`	`master_config.ctarConfig.direction = kDSPI_MsbFirst;`
`93`		`- master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;`
	`93`	`+ master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;`
`94`	`94`
`95`	`95`	`DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance]));`
`96`	`96`	`}`
`@@ -104,7 +104,7 @@ void spi_frequency(spi_t *obj, int hz)`
`104`	`104`	`DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);`
`105`	`105`	`}`
`106`	`106`
`107`		`-static inline int spi_readable(spi_t * obj)`
	`107`	`+static inline int spi_readable(spi_t *obj)`
`108`	`108`	`{`
`109`	`109`	`return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag);`
`110`	`110`	`}`
`@@ -314,14 +314,14 @@ static void spi_buffer_set(spi_t obj, const void tx, uint32_t tx_length, void`
`314`	`314`
`315`	`315`	`void spi_master_transfer(spi_t obj, const void tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)`
`316`	`316`	`{`
`317`		`- if(spi_active(obj)) {`
	`317`	`+ if (spi_active(obj)) {`
`318`	`318`	`return;`
`319`	`319`	`}`
`320`	`320`
`321`	`321`	`/* check corner case */`
`322`		`- if(tx_length == 0) {`
	`322`	`+ if (tx_length == 0) {`
`323`	`323`	`tx_length = rx_length;`
`324`		`- tx = (void*) 0;`
	`324`	`+ tx = (void *) 0;`
`325`	`325`	`}`
`326`	`326`
`327`	`327`	`/* First, set the buffer */`
`@@ -422,7 +422,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)`
`422`	`422`	`void spi_abort_asynch(spi_t *obj)`
`423`	`423`	`{`
`424`	`424`	`// If we're not currently transferring, then there's nothing to do here`
`425`		`- if(spi_active(obj) == 0) {`
	`425`	`+ if (spi_active(obj) == 0) {`
`426`	`426`	`return;`
`427`	`427`	`}`
`428`	`428`