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jeromecoutantLMESTM
jeromecoutant
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LMESTM
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STM32L4: Add OSPI IP support in fallback QSPI mode
For STM32 platforms that embed an OSPI IP, we're offering a QSPI fallback support with this commit. When OSPI is supported in mbed, we can consider adding full OSPI support
1 parent 4f22a10 commit 5c33726

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8 files changed

+543
-53
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8 files changed

+543
-53
lines changed

‎components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json

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@@ -34,6 +34,9 @@
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"DISCO_F769NI": {
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"QSPI_FREQ": "8000000"
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},
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"DISCO_L4R9I": {
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"QSPI_FREQ": "84000000"
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},
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"MCU_NRF52840": {
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"QSPI_FREQ": "32000000",
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"QSPI_MIN_READ_SIZE": "4",

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralNames.h

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@@ -83,6 +83,11 @@ typedef enum {
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CAN_1 = (int)CAN1_BASE
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} CANName;
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typedef enum {
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QSPI_1 = (int)OCTOSPI1_R_BASE,
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QSPI_2 = (int)OCTOSPI2_R_BASE
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} QSPIName;
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c

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@@ -390,3 +390,59 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
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{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D9
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{NC, NC, 0}
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};
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//*** QUADSPI ***
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MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
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{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0
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{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 // Connected to D9
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{PF_0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 // Connected to PSRAM_A0
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{PI_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 // Connected to OCTOSPIM_P2_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
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{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to ARD_A3
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{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to D10
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{PF_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 // Connected to PSRAM_A1
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{PI_10, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 // Connected to OCTOSPIM_P2_IO1
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
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{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to ARD_A0
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{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to D11
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{PF_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 // Connected to PSRAM_A2
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{PI_9, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 // Connected to OCTOSPIM_P2_IO2
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
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{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to SPI2_CS
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{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to D12
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{PF_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 // Connected to PSRAM_A3
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{PH_8, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 // Connected to OCTOSPI_P2_IO3
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
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// {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to STDIO_UART_RX
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{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to USART3_TX
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{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to D7
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{PF_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK // Connected to PSRAM_A4
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{PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
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{PI_6, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK // Connected to OCTOSPIM_P2_CLK
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
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// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to STDIO_UART_TX
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{PA_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to DCMI_HSYNC
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{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to USART3_RX
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{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to uSD_D3
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{PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to PSRAM_CLK
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{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to D8
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{PG_12, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to OCTOSPIM_P2_CS
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{PI_5, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to DCMI_VSYNC
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{NC, NC, 0}
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};

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h

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@@ -352,6 +352,14 @@ typedef enum {
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SYS_WKUP3 = PE_6,
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SYS_WKUP4 = PA_2,
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/**** QSPI FLASH pins ****/
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QSPI_FLASH1_IO0 = PI_11,
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QSPI_FLASH1_IO1 = PI_10,
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QSPI_FLASH1_IO2 = PI_9,
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QSPI_FLASH1_IO3 = PH_8,
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QSPI_FLASH1_SCK = PI_6,
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QSPI_FLASH1_CSN = PG_12,
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/**** STMOD+ pins ****/
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STMOD_1 = PA_6,
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STMOD_2 = PB_15,

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/objects.h

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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/objects.h

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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2019, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifndef MBED_OBJECTS_H
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#define MBED_OBJECTS_H
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#include "cmsis.h"
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#include "PortNames.h"
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#include "PeripheralNames.h"
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#include "PinNames.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct gpio_irq_s {
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IRQn_Type irq_n;
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uint32_t irq_index;
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uint32_t event;
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PinName pin;
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};
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struct port_s {
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PortName port;
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uint32_t mask;
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PinDirection direction;
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__IO uint32_t *reg_in;
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__IO uint32_t *reg_out;
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};
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struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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OSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus
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}
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#endif
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#endif

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