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Deepika
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ARMC6 support for Cortex-M23
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‎rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S

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;/*
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; * Copyright (c) 2016 ARM Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; *
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; * -----------------------------------------------------------------------------
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; *
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; * Project: CMSIS-RTOS RTX
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; * Title: ARMv8M Baseline Exception handlers
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; *
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; * -----------------------------------------------------------------------------
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; */
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I_T_RUN_OFS EQU 28 ; osInfo.thread.run offset
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TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
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TCB_SP_OFS EQU 56 ; TCB.SP offset
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TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
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TCB_TZM_OFS EQU 60 ; TCB.tz_memory offset
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PRESERVE8
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THUMB
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AREA |.constdata|, DATA, READONLY
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EXPORT os_irq_cm
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os_irq_cm DCB 0 ; Non weak library reference
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AREA |.text|, CODE, READONLY
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SVC_Handler PROC
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EXPORT SVC_Handler
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IMPORT os_UserSVC_Table
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IMPORT os_Info
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#ifdef __DOMAIN_NS
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IMPORT TZ_LoadContext_S
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IMPORT TZ_StoreContext_S
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#endif
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MRS R0,PSP ; Get PSP
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LDR R1,[R0,#24] ; Load saved PC from stack
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SUBS R1,R1,#2 ; Point to SVC instruction
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LDRB R1,[R1] ; Load SVC number
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CMP R1,#0
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BNE SVC_User ; Branch if not SVC 0
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PUSH {R0,LR} ; Save PSP and EXC_RETURN
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LDM R0,{R0-R3} ; Load function parameters from stack
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BLX R7 ; Call service function
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POP {R2,R3} ; Restore PSP and EXC_RETURN
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STMIA R2!,{R0-R1} ; Store function return values
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MOV LR,R3 ; Set EXC_RETURN
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SVC_Context
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LDR R3,=os_Info+I_T_RUN_OFS; Load address of os_Info.run
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LDMIA R3!,{R1,R2} ; Load os_Info.thread.run: curr & next
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CMP R1,R2 ; Check if thread switch is required
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BEQ SVC_Exit ; Branch when threads are the same
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CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
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SVC_ContextSave
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#ifdef __DOMAIN_NS
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LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
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PUSH {R1,R2,R3,R7} ; Save registers
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MOV R7,LR ; Get EXC_RETURN
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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#endif
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SVC_ContextSave1
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MRS R0,PSP ; Get PSP
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SUBS R0,R0,#32 ; Adjust PSP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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STMIA R0!,{R4-R7} ; Save R4..R7
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save R8..R11
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SVC_ContextSave2
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MOV R0,LR ; Get EXC_RETURN
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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STRB R0,[R1] ; Store stack frame information
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SVC_ContextSwitch
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SUBS R3,R3,#8 ; Adjust address
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STR R2,[R3] ; os_Info.thread.run: curr = next
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SVC_ContextRestore
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#ifdef __DOMAIN_NS
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LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
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PUSH {R2,R3} ; Save registers
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BL TZ_LoadContext_S ; Load secure context
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POP {R2,R3} ; Restore registers
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#endif
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SVC_ContextRestore1
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MOV R1,R2
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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LDRB R0,[R1] ; Load stack frame information
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MOVS R1,#0xFF
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MVNS R1,R1 ; R1=0xFFFFFF00
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ORRS R0,R1
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MOV LR,R0 ; Set EXC_RETURN
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#ifdef __DOMAIN_NS
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL SVC_ContextRestore2 ; Branch if non-secure
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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MSR PSP,R0 ; Set PSP
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BX LR ; Exit from handler
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#else
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LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
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MSR PSPLIM,R0 ; Set PSPLIM
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#endif
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SVC_ContextRestore2
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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ADDS R0,R0,#16 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R8..R11
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Set PSP
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SUBS R0,R0,#32 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R4..R7
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SVC_Exit
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BX LR ; Exit from handler
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SVC_User
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PUSH {R4,LR} ; Save registers
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LDR R2,=os_UserSVC_Table ; Load address of SVC table
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LDR R3,[R2] ; Load SVC maximum number
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CMP R1,R3 ; Check SVC number range
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BHI SVC_Done ; Branch if out of range
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LSLS R1,R1,#2
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LDR R4,[R2,R1] ; Load address of SVC function
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LDM R0,{R0-R3} ; Load function parameters from stack
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BLX R4 ; Call service function
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MRS R4,PSP ; Get PSP
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STR R0,[R4] ; Store function return value
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SVC_Done
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POP {R4,PC} ; Return from handler
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ALIGN
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler
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IMPORT os_PendSV_Handler
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PUSH {R0,LR} ; Save EXC_RETURN
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BL os_PendSV_Handler ; Call os_PendSV_Handler
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POP {R0,R1} ; Restore EXC_RETURN
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MOV LR,R1 ; Set EXC_RETURN
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B Sys_Context
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ALIGN
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler
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IMPORT os_Tick_Handler
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PUSH {R0,LR} ; Save EXC_RETURN
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BL os_Tick_Handler ; Call os_Tick_Handler
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POP {R0,R1} ; Restore EXC_RETURN
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MOV LR,R1 ; Set EXC_RETURN
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B Sys_Context
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ALIGN
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ENDP
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Sys_Context PROC
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EXPORT Sys_Context
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IMPORT os_Info
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#ifdef __DOMAIN_NS
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IMPORT TZ_LoadContext_S
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IMPORT TZ_StoreContext_S
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#endif
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LDR R3,=os_Info+I_T_RUN_OFS; Load address of os_Info.run
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LDM R3!,{R1,R2} ; Load os_Info.thread.run: curr & next
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CMP R1,R2 ; Check if thread switch is required
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BEQ Sys_ContextExit ; Branch when threads are the same
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Sys_ContextSave
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#ifdef __DOMAIN_NS
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LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
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PUSH {R1,R2,R3,R7} ; Save registers
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MOV R7,LR ; Get EXC_RETURN
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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LSLS R7,R7,#25 ; Check domain of interrupted thread
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BMI Sys_ContextSave1 ; Branch if secure
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MRS R0,PSP ; Get PSP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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B Sys_ContextSave2
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#endif
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Sys_ContextSave1
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MRS R0,PSP ; Get PSP
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SUBS R0,R0,#32 ; Adjust address
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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STMIA R0!,{R4-R7} ; Save R4..R7
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save R8..R11
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Sys_ContextSave2
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MOV R0,LR ; Get EXC_RETURN
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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STRB R0,[R1] ; Store stack frame information
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Sys_ContextSwitch
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SUBS R3,R3,#8 ; Adjust address
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STR R2,[R3] ; os_Info.run: curr = next
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Sys_ContextRestore
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#ifdef __DOMAIN_NS
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LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
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PUSH {R2,R3} ; Save registers
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BL TZ_LoadContext_S ; Load secure context
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POP {R2,R3} ; Restore registers
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#endif
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Sys_ContextRestore1
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MOV R1,R2
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ADDS R1,R1,#TCB_SF_OFS ; Adjust offset
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LDRB R0,[R1] ; Load stack frame information
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MOVS R1,#0xFF
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MVNS R1,R1 ; R1=0xFFFFFF00
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ORRS R0,R1
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MOV LR,R0 ; Set EXC_RETURN
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#ifdef __DOMAIN_NS
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL Sys_ContextRestore2 ; Branch if non-secure
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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MSR PSP,R0 ; Set PSP
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BX LR ; Exit from handler
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#else
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LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
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MSR PSPLIM,R0 ; Set PSPLIM
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#endif
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Sys_ContextRestore2
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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ADDS R0,R0,#16 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R8..R11
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Set PSP
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SUBS R0,R0,#32 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R4..R7
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Sys_ContextExit
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BX LR ; Exit from handler
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ALIGN
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ENDP
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END

‎tools/toolchains/arm.py

Lines changed: 13 additions & 1 deletion
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@@ -285,6 +285,9 @@ def __init__(self, target, *args, **kwargs):
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elif target.core.lower().endswith("f"):
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self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1])
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self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1])
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elif target.core.lower().endswith("ns"):
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self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-3])
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self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-3])
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else:
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self.flags['common'].append("-mcpu=%s" % target.core.lower())
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self.flags['ld'].append("--cpu=%s" % target.core.lower())
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elif target.core == "Cortex-M7FD":
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self.flags['common'].append("-mfpu=fpv5-d16")
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self.flags['common'].append("-mfloat-abi=softfp")
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elif target.core.startswith("Cortex-M23"):
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self.flags['common'].append("-march=armv8-m.base")
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elif target.core.startswith("Cortex-M33"):
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self.flags['common'].append("-march=armv8-m.main")
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if target.core == "Cortex-M23" or target.core == "Cortex-M33":
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self.flags['common'].append("-mcmse")
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asm_cpu = {
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"Cortex-M0+": "Cortex-M0",
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"Cortex-M4F": "Cortex-M4.fp",
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"Cortex-M7F": "Cortex-M7.fp.sp",
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"Cortex-M7FD": "Cortex-M7.fp.dp"}.get(target.core, target.core)
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"Cortex-M7FD": "Cortex-M7.fp.dp",
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"Cortex-M23-NS": "Cortex-M23",
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"Cortex-M33-NS": "Cortex-M33" }.get(target.core, target.core)
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308320
self.flags['asm'].append("--cpu=%s" % asm_cpu)
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