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adding flash support
adding flash support Updated SDK 2.9.1 and added Flash Support
1 parent 0f4bc86 commit 659f0bb

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3 files changed

+17
-246
lines changed

3 files changed

+17
-246
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/device.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,10 +23,10 @@
2323

2424

2525

26-
#define BOARD_FLASH_SIZE (0x800000U)
27-
#define BOARD_FLASH_START_ADDR (0x60000000U)
28-
#define BOARD_FLASHIAP_SIZE (0x7F0000U)
29-
#define BOARD_FLASHIAP_START_ADDR (0x60010000U)
26+
#define BOARD_FLASH_SIZE (0x1000000U)
27+
#define BOARD_FLASH_START_ADDR (0x30000000U)
28+
#define BOARD_FLASHIAP_SIZE (0xFF0000U)
29+
#define BOARD_FLASHIAP_START_ADDR (0x30010000U)
3030
#define BOARD_FLASH_PAGE_SIZE (256)
3131
#define BOARD_FLASH_SECTOR_SIZE (4096)
3232

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/flash_api.c

Lines changed: 2 additions & 241 deletions
Original file line numberDiff line numberDiff line change
@@ -84,243 +84,6 @@ void *flexspi_memset(void *buf, int c, size_t n)
8484
return buf;
8585
}
8686

87-
#ifdef HYPERFLASH_BOOT
88-
AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void));
89-
AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void));
90-
void flexspi_update_lut_ram(void)
91-
{
92-
flexspi_config_t config;
93-
94-
flexspi_memset(&config, 0, sizeof(config));
95-
96-
/*Get FLEXSPI default settings and configure the flexspi. */
97-
FLEXSPI_GetDefaultConfig(&config);
98-
99-
/*Set AHB buffer size for reading data through AHB bus. */
100-
config.ahbConfig.enableAHBPrefetch = true;
101-
/*Allow AHB read start address do not follow the alignment requirement. */
102-
config.ahbConfig.enableReadAddressOpt = true;
103-
config.ahbConfig.enableAHBBufferable = true;
104-
config.ahbConfig.enableAHBCachable = true;
105-
/* enable diff clock and DQS */
106-
config.enableSckBDiffOpt = true;
107-
config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
108-
config.enableCombination = true;
109-
FLEXSPI_Init(FLEXSPI, &config);
110-
111-
/* Configure flash settings according to serial flash feature. */
112-
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
113-
114-
/* Update LUT table. */
115-
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
116-
117-
FLEXSPI_SoftwareReset(FLEXSPI);
118-
119-
/* Wait for bus idle. */
120-
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
121-
}
122-
}
123-
124-
status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
125-
{
126-
flexspi_transfer_t flashXfer;
127-
status_t status = kStatus_Success;
128-
129-
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
130-
131-
/* Write enable */
132-
flashXfer.deviceAddress = baseAddr;
133-
flashXfer.port = kFLEXSPI_PortA1;
134-
flashXfer.cmdType = kFLEXSPI_Command;
135-
flashXfer.SeqNumber = 2;
136-
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
137-
138-
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
139-
140-
return status;
141-
}
142-
143-
status_t flexspi_nor_wait_bus_busy_ram(void)
144-
{
145-
/* Wait status ready. */
146-
bool isBusy = false;
147-
uint32_t readValue = 0;
148-
status_t status = kStatus_Success;
149-
flexspi_transfer_t flashXfer;
150-
151-
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
152-
153-
flashXfer.deviceAddress = 0;
154-
flashXfer.port = kFLEXSPI_PortA1;
155-
flashXfer.cmdType = kFLEXSPI_Read;
156-
flashXfer.SeqNumber = 2;
157-
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
158-
flashXfer.data = &readValue;
159-
flashXfer.dataSize = 2;
160-
161-
do {
162-
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
163-
164-
if (status != kStatus_Success) {
165-
return status;
166-
}
167-
168-
if (readValue & 0x8000) {
169-
isBusy = false;
170-
} else {
171-
isBusy = true;
172-
}
173-
174-
if (readValue & 0x3200) {
175-
status = kStatus_Fail;
176-
break;
177-
}
178-
179-
} while (isBusy);
180-
181-
return status;
182-
183-
}
184-
185-
status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
186-
{
187-
status_t status = kStatus_Success;
188-
flexspi_transfer_t flashXfer;
189-
190-
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
191-
192-
/* Write enable */
193-
status = flexspi_nor_write_enable_ram(address);
194-
if (status != kStatus_Success) {
195-
return status;
196-
}
197-
198-
flashXfer.deviceAddress = address;
199-
flashXfer.port = kFLEXSPI_PortA1;
200-
flashXfer.cmdType = kFLEXSPI_Command;
201-
flashXfer.SeqNumber = 4;
202-
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
203-
204-
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
205-
if (status != kStatus_Success) {
206-
return status;
207-
}
208-
209-
status = flexspi_nor_wait_bus_busy_ram();
210-
211-
/* Do software reset. */
212-
FLEXSPI_SoftwareReset(FLEXSPI);
213-
214-
return status;
215-
}
216-
217-
void flexspi_lower_clock_ram(void)
218-
{
219-
unsigned int reg = 0;
220-
221-
/* Wait for bus idle. */
222-
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
223-
}
224-
225-
FLEXSPI_Enable(FLEXSPI, false);
226-
227-
/* Disable FlexSPI clock */
228-
CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
229-
230-
/* flexspi clock 66M, DDR mode, internal clock 33M. */
231-
reg = CCM->CSCMR1;
232-
reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
233-
reg |= CCM_CSCMR1_FLEXSPI_PODF(3);
234-
CCM->CSCMR1 = reg;
235-
236-
/* Enable FlexSPI clock */
237-
CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
238-
239-
FLEXSPI_Enable(FLEXSPI, true);
240-
241-
/* Do software reset. */
242-
FLEXSPI_SoftwareReset(FLEXSPI);
243-
244-
/* Wait for bus idle. */
245-
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
246-
}
247-
}
248-
249-
void flexspi_clock_update_ram(void)
250-
{
251-
/* Program finished, speed the clock to 133M. */
252-
/* Wait for bus idle before change flash configuration. */
253-
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
254-
}
255-
FLEXSPI_Enable(FLEXSPI, false);
256-
/* Disable FlexSPI clock */
257-
CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
258-
259-
/* flexspi clock 260M, DDR mode, internal clock 130M. */
260-
CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
261-
262-
/* Enable FlexSPI clock */
263-
CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
264-
265-
FLEXSPI_Enable(FLEXSPI, true);
266-
267-
/* Do software reset. */
268-
FLEXSPI_SoftwareReset(FLEXSPI);
269-
270-
/* Wait for bus idle. */
271-
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
272-
}
273-
}
274-
275-
status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
276-
{
277-
status_t status = kStatus_Success;
278-
flexspi_transfer_t flashXfer;
279-
uint32_t offset = 0;
280-
281-
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
282-
283-
flexspi_lower_clock_ram();
284-
285-
while (size > 0) {
286-
/* Write enable */
287-
status = flexspi_nor_write_enable_ram(address + offset);
288-
289-
if (status != kStatus_Success) {
290-
return status;
291-
}
292-
293-
/* Prepare page program command */
294-
flashXfer.deviceAddress = address + offset;
295-
flashXfer.port = kFLEXSPI_PortA1;
296-
flashXfer.cmdType = kFLEXSPI_Write;
297-
flashXfer.SeqNumber = 2;
298-
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
299-
flashXfer.data = (uint32_t *)((uint32_t)src + offset);
300-
flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE;
301-
302-
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
303-
304-
if (status != kStatus_Success) {
305-
return status;
306-
}
307-
308-
status = flexspi_nor_wait_bus_busy_ram();
309-
310-
if (status != kStatus_Success) {
311-
return status;
312-
}
313-
314-
size -= BOARD_FLASH_PAGE_SIZE;
315-
offset += BOARD_FLASH_PAGE_SIZE;
316-
}
317-
318-
flexspi_clock_update_ram();
319-
320-
return status;
321-
}
322-
323-
#else
32487
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
32588
status_t flexspi_nor_enable_quad_mode_ram(void)
32689
{
@@ -373,7 +136,6 @@ void flexspi_update_lut_ram(void)
373136
config.ahbConfig.enableReadAddressOpt = true;
374137
config.ahbConfig.enableAHBCachable = true;
375138
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
376-
FLEXSPI_Init(FLEXSPI, &config);
377139

378140
/* Configure flash settings according to serial flash feature. */
379141
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
@@ -537,7 +299,6 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr
537299
return status;
538300
}
539301

540-
#endif
541302
void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
542303
{
543304
memcpy(buffer, (void *)addr, size);
@@ -607,8 +368,8 @@ int32_t flash_free(flash_t *obj)
607368
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
608369
{
609370
uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
610-
uint32_t devicesize = BOARD_FLASH_SIZE;
611-
uint32_t startaddr = BOARD_FLASH_START_ADDR;
371+
uint32_t devicesize = BOARD_FLASHIAP_SIZE;
372+
uint32_t startaddr = BOARD_FLASHIAP_START_ADDR;
612373

613374
if ((address >= startaddr) && (address < (startaddr + devicesize))) {
614375
sectorsize = BOARD_FLASH_SECTOR_SIZE;

‎targets/targets.json

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4402,11 +4402,17 @@
44024402
"is_disk_virtual": true,
44034403
"macros": [
44044404
"CPU_MIMXRT1176DVMAA_cm7",
4405+
"FSL_RTOS_MBED",
44054406
"XIP_BOOT_HEADER_ENABLE=1",
44064407
"XIP_EXTERNAL_FLASH=1",
44074408
"XIP_BOOT_HEADER_DCD_ENABLE=1",
44084409
"SKIP_SYSCLK_INIT",
4409-
"MBED_MPU_CUSTOM"
4410+
"MBED_MPU_CUSTOM",
4411+
"FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1",
4412+
"__STARTUP_INITIALIZE_RAMFUNCTION",
4413+
"__STARTUP_INITIALIZE_NONCACHEDATA",
4414+
"MBED_TICKLESS",
4415+
"DATA_SECTION_IS_CACHEABLE=1"
44104416
],
44114417
"inherits": [
44124418
"Target"
@@ -4416,6 +4422,7 @@
44164422
],
44174423
"device_has": [
44184424
"ANALOGIN",
4425+
"FLASH",
44194426
"INTERRUPTIN",
44204427
"I2C",
44214428
"I2CSLAVE",
@@ -4426,6 +4433,9 @@
44264433
"LPTICKER",
44274434
"USTICKER"
44284435
],
4436+
"release_versions": [
4437+
"5"
4438+
],
44294439
"supported_application_profiles" : ["full", "bare-metal"],
44304440
"supported_c_libs": {
44314441
"arm": [

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