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dustin-crossmandustin-crossman
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Update cypress targets.
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64 files changed

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lines changed

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
8585
cy_rslt_t result = CY_RSLT_SUCCESS;
8686
#endif
8787

88-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
88+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
8989
init_cycfg_all();
9090
#endif
9191

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
#include "cy_result.h"
2828
#include "cybsp_types.h"
29-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
29+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
3030
#include "cycfg.h"
3131
#endif
3232
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
8585
cy_rslt_t result = CY_RSLT_SUCCESS;
8686
#endif
8787

88-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
88+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
8989
init_cycfg_all();
9090
#endif
9191

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
#include "cy_result.h"
2828
#include "cybsp_types.h"
29-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
29+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
3030
#include "cycfg.h"
3131
#endif
3232
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
8585
cy_rslt_t result = CY_RSLT_SUCCESS;
8686
#endif
8787

88-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
88+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
8989
init_cycfg_all();
9090
#endif
9191

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
#include "cy_result.h"
2828
#include "cybsp_types.h"
29-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
29+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
3030
#include "cycfg.h"
3131
#endif
3232
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
8585
cy_rslt_t result = CY_RSLT_SUCCESS;
8686
#endif
8787

88-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
88+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
8989
init_cycfg_all();
9090
#endif
9191

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
#include "cy_result.h"
2828
#include "cybsp_types.h"
29-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
29+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
3030
#include "cycfg.h"
3131
#endif
3232
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Wrapper function to initialize all generated code.
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Simple wrapper header containing all generated files.
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Sentinel file for determining if generated source is up to date.
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* design.
77
* This file was automatically generated and should not be modified.
88
* Device Configurator: 2.0.0.1483
9-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
9+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
1010
*
1111
********************************************************************************
1212
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Establishes all necessary connections between hardware elements.
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Establishes all necessary connections between hardware elements.
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -38,13 +38,13 @@ void init_cycfg_routing(void);
3838
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
3939
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
4040
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
41-
#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA
41+
#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXB
4242
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
43-
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
44-
#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
45-
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
46-
#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
47-
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
43+
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
44+
#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXB
45+
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
46+
#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXB
47+
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
4848
#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXB
4949

5050
#if defined(__cplusplus)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* System configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -242,14 +242,14 @@ __STATIC_INLINE void init_cycfg_power(void)
242242
{
243243
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
244244
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
245+
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
245246
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
246247
{
247248
Cy_SysLib_ResetBackupDomain();
248249
Cy_SysClk_IloDisable();
249250
Cy_SysClk_IloInit();
250251
}
251-
#else /* Dedicated Supply */
252-
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
252+
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
253253
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
254254

255255
/* Configure core regulator */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* System configuration
66
* This file was automatically generated and should not be modified.
77
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
8+
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
<?xml version="1.0" encoding="UTF-8"?>
2-
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
2+
<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
33
<ToolInfo version="1.0.0"/>
44
<Devices>
55
<Device mpn="CY8C6245LQI-S3D72">

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
8585
cy_rslt_t result = CY_RSLT_SUCCESS;
8686
#endif
8787

88-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
88+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
8989
init_cycfg_all();
9090
#endif
9191

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
#include "cy_result.h"
2828
#include "cybsp_types.h"
29-
#if defined(COMPONENT_BSP_DESIGN_MODUS)
29+
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
3030
#include "cycfg.h"
3131
#endif
3232
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Wrapper function to initialize all generated code.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Simple wrapper header containing all generated files.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Sentinel file for determining if generated source is up to date.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
* Contains warnings and errors that occurred while generating code for the
66
* design.
77
* This file was automatically generated and should not be modified.
8-
* cfg-backend-cli: 1.2.0.1478
8+
* Device Configurator: 2.0.0.1483
99
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
1010
*
1111
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************
@@ -38,7 +38,7 @@ extern "C" {
3838
#define CYBSP_CSD_ENABLED 1U
3939
#define CY_CAPSENSE_CORE 4u
4040
#define CY_CAPSENSE_CPU_CLK 100000000u
41-
#define CY_CAPSENSE_PERI_CLK 50000000u
41+
#define CY_CAPSENSE_PERI_CLK 100000000u
4242
#define CY_CAPSENSE_VDDA_MV 3300u
4343
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
4444
#define CY_CAPSENSE_PERI_DIV_INDEX 0u

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Establishes all necessary connections between hardware elements.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Description:
55
* Establishes all necessary connections between hardware elements.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
7+
* Device Configurator: 2.0.0.1483
88
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
99
*
1010
********************************************************************************
@@ -42,12 +42,12 @@ void init_cycfg_routing(void);
4242
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
4343
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
4444
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
45-
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
45+
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
4646
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
4747
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
4848
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
4949
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
50-
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
50+
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
5151
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
5252
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
5353

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