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Merge pull request #12615 from jeromecoutant/PR_FPGA_UART
FPGA UART test cases addition with 7 and 9 bits data length
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‎TESTS/configs/fpga.json

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,8 @@
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},
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"K64F": {
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"target.macros_add": [
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"UART_7BITS_PARITY_NONE_NOT_SUPPORTED"
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"UART_7BITS_NOT_SUPPORTED",
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"UART_9BITS_NOT_SUPPORTED"
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]
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},
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"STM": {

‎TESTS/mbed_hal_fpga_ci_test_shield/README.md

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@@ -0,0 +1,51 @@
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# Testing with FPGA CI TEST shield
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## Setup
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![30% center](fpga_test_shield.jpg)
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```
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mbed test -n tests*fpga* --app-config tests/configs/fpga.json
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```
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FPGA_CI_TEST_SHIELD needed macro
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and specific test capabilities per target
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are defined in:
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https://github.com/ARMmbed/mbed-os/blob/master/TESTS/configs/fpga.json
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## MBED-OS
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Tested from factor is defined by MBED_CONF_TARGET_DEFAULT_FORM_FACTOR
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"default-form-factor" default value is null.
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When "default-form-factor" is not set, ARDUINO form factor is used.
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Default ff_arduino_pins is defined in:
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https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L28-L32
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Default ff_arduino_names is defined in:
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https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L34-L38
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Default empty_gpio_pinmap is defined in:
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https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_gpio.c#L89-L114
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Some pins are restricted:
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https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L69-L73
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Some peripherals are restricted:
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https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L94-L100
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## Known issues
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## LINKS
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https://github.com/ARMmbed/fpga-ci-test-shield
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https://github.com/ARMmbed/fpga-ci-test-shield-updater
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https://github.com/ARMmbed/fpga-ci-test-shield-terminal
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‎TESTS/mbed_hal_fpga_ci_test_shield/fpga_test_shield.jpg

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‎TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp

Lines changed: 44 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,16 +86,37 @@ static void test_irq_handler(uint32_t id, SerialIrq event)
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static void uart_test_common(int baudrate, int data_bits, SerialParity parity, int stop_bits, bool init_direct, PinName tx, PinName rx, PinName cts, PinName rts)
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{
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// The FPGA CI shield only supports None, Odd & Even.
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// Forced parity is not supported on Atmel, Freescale, Nordic & STM targets.
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// Forced parity is not supported on many targets
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MBED_ASSERT(parity != ParityForced1 && parity != ParityForced0);
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// STM-specific constraints
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// Only 7, 8 & 9 data bits.
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MBED_ASSERT(data_bits >= 7 && data_bits <= 9);
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// Only Odd or Even parity for 7 data bits.
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// See TESTS/configs/fpga.json to check which target supports what
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#if defined(UART_9BITS_NOT_SUPPORTED)
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if (data_bits == 9) {
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utest_printf(" UART_9BITS_NOT_SUPPORTED set ... ");
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return;
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}
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#endif
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#if defined(UART_9BITS_PARITY_NOT_SUPPORTED)
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if ((data_bits == 9) && (parity != ParityNone)) {
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utest_printf(" UART_9BITS_PARITY_NOT_SUPPORTED set ... ");
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return;
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}
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#endif
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#if defined(UART_7BITS_NOT_SUPPORTED)
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if (data_bits == 7) {
97-
MBED_ASSERT(parity != ParityNone);
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utest_printf(" UART_7BITS_NOT_SUPPORTED set ... ");
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return;
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}
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#endif
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#if defined(UART_7BITS_PARITY_NONE_NOT_SUPPORTED)
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if ((data_bits == 7) && (parity == ParityNone)) {
116+
utest_printf(" UART_7BITS_PARITY_NONE_NOT_SUPPORTED set ... ");
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return;
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}
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#endif
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// Limit the actual TX & RX chars to 8 bits for this test.
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int test_buff_bits = data_bits < 8 ? data_bits : 8;
@@ -333,6 +354,10 @@ Case cases[] = {
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Case("basic, 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 1, false> >),
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Case("basic (direct init), 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 1, true> >),
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// same test with 7 and 9 bits data length
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Case("basic, 9600, 7N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 7, ParityNone, 1, false> >),
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Case("basic, 9600, 9N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 9, ParityNone, 1, false> >),
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// One set of pins from one peripheral.
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// baudrate
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Case("19200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<19200, 8, ParityNone, 1, false> >),
@@ -351,6 +376,10 @@ Case cases[] = {
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Case("basic, 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 1, false> >),
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Case("basic (direct init), 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 1, true> >),
353378

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// same test with 7 and 9 bits data length
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Case("basic, 9600, 7N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityNone, 1, false> >),
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Case("basic, 9600, 9N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityNone, 1, false> >),
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// One set of pins from one peripheral.
355384
// baudrate
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Case("19200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<19200, 8, ParityNone, 1, false> >),
@@ -360,8 +389,17 @@ Case cases[] = {
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// parity
361390
#if !defined(UART_ODD_PARITY_NOT_SUPPORTED)
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Case("9600, 8O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityOdd, 1, false> >),
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// same test with 7 and 9 bits data length
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Case("9600, 7O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityOdd, 1, false> >),
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Case("9600, 9O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityOdd, 1, false> >),
363396
#endif
364397
Case("9600, 8E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityEven, 1, false> >),
398+
399+
// same test with 7 and 9 bits data length
400+
Case("9600, 7E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityEven, 1, false> >),
401+
Case("9600, 9E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityEven, 1, false> >),
402+
365403
// stop bits
366404
#if !defined(UART_TWO_STOP_BITS_NOT_SUPPORTED)
367405
Case("9600, 8N2, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 2, false> >),

‎targets/targets.json

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@@ -5640,9 +5640,7 @@
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"WSF_MAX_HANDLERS=10",
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"MBED_MPU_CUSTOM",
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"SWI_DISABLE0",
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"NRF52_PAN_20",
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"UART_TWO_STOP_BITS_NOT_SUPPORTED",
5645-
"UART_ODD_PARITY_NOT_SUPPORTED"
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"NRF52_PAN_20"
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],
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"features": [
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"CRYPTOCELL310",

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