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Add MT25Q Flash config
Signed-off-by: Maciej Bociański <[email protected]> Signed-off-by: Mahesh Mahadevan <[email protected]>
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‎TESTS/mbed_hal/qspi/flash_configs/MT25Q_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_MT25Q_H
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#define MBED_QSPI_FLASH_MT25Q_H
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#define QSPI_FLASH_CHIP_STRING "Micron MT25Q"
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// Command for reading status register
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#define QSPI_CMD_RDSR 0x05
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// Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_RDCR0 0xB5
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// Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_RDCR1 0x85
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// Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_RDCR2 0x65
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// Command for writing status register
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#define QSPI_CMD_WRSR 0x01
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// Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_WRCR0 0xB1
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// Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_WRCR1 0x81
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// Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
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#define QSPI_CMD_WRCR2 0x61
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// Command for setting Reset Enable
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#define QSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define QSPI_CMD_RST 0x99
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// Command for setting write enable
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#define QSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define QSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define QSPI_WRSR_MAX_TIME 9200 // 8ms
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// general wait max time [us]
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#define QSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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#define QSPI_CMD_WRITE_1I2O 0xA2 // 1-1-2 mode
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#define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
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#define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode
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#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
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#define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
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#define QSPI_CMD_WRITE_QPI 0x38 // 4-4-4 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define QSPI_PAGE_PROG_MAX_TIME 2070 // 1.8ms
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#define QSPI_PAGE_SIZE 256 // 256B
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#define QSPI_SECTOR_SIZE 4096 // 4kB
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#define QSPI_SECTOR_COUNT 4096 // for 128Mb chip
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// Commands for reading
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#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
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#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
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#define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
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#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
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#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
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#define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
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#define QSPI_READ_1IO_DUMMY_CYCLE 0 // 1-1-1 mode
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#define QSPI_READ_FAST_DUMMY_CYCLE 8 // 1-1-1 mode
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#define QSPI_READ_1I2O_DUMMY_CYCLE 8 // 1-1-2 mode
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#define QSPI_READ_2IO_DUMMY_CYCLE 8 // 1-2-2 mode
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#define QSPI_READ_DPI_DUMMY_CYCLE 8 // 2-2-2 mode
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#define QSPI_READ_1I4O_DUMMY_CYCLE 8 // 1-1-4 mode
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#define QSPI_READ_4IO_DUMMY_CYCLE 10 // 1-4-4 mode
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#define QSPI_READ_QPI_DUMMY_CYCLE 10 // 4-4-4 mode
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
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#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
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#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define QSPI_ERASE_SECTOR_MAX_TIME 460000 // 0.4s
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 1150000 // 1s
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// max frequency for basic rw operation
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#define QSPI_COMMON_MAX_FREQUENCY 50000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 2
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#define QSPI_CONFIG_REG_1_SIZE 1
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#define QSPI_CONFIG_REG_2_SIZE 1
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#define QSPI_MAX_REG_SIZE 2
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) // Block protect
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#define STATUS_BIT_BP1 (1 << 3) // Block protect
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#define STATUS_BIT_BP2 (1 << 4) // Block protect
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#define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
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#define STATUS_BIT_BP3 (1 << 6) // Block protect
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#define STATUS_BIT_SRWD (1 << 7) // status register write protect
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// configuration register 0 (Nonvolatile Configuration Register)
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// bit 0, 1 reserved
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#define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
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#define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
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#define CONFIG0_BIT_RH (1 << 4) // Reset/hold
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#define CONFIG0_BIT_DTR (1 << 5) // Double transfer rate protocol
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#define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
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#define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
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#define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
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#define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
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#define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
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#define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
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#define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
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#define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
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#define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
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#define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
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// configuration register 1 (Volatile Configuration Register)
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// bit 2, reserved
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#define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
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#define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
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#define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
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#define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
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#define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
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#define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
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#define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
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// configuration register 2 (Enhanced Volatile Configuration Register)
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// bit 3, reserved
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#define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
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#define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
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#define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
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#define CONFIG2_BIT_RH (1 << 4) // Reset/hold
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#define CONFIG2_BIT_DTR (1 << 5) // Double transfer rate protocol
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#define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
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#define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
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#define DUAL_ENABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
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if (write_register(QSPI_CMD_WRCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define DUAL_DISABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
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if (write_register(QSPI_CMD_WRCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define QUAD_ENABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
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if (write_register(QSPI_CMD_WRCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define QUAD_DISABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
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if (write_register(QSPI_CMD_WRCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
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if (read_register(QSPI_CMD_RDCR2, reg_data, \
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QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#endif // MBED_QSPI_FLASH_MT25Q_H
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