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Merge pull request #13122 from romanjoe/pr/add_cy8ckit_064b0b2_4343w
Cypress: Add target CY8CKIT_064B0S2_4343W, update psoc6pdl, psoc6cm0p
2 parents b4389c7 + 00cbc2d commit 6c27da5

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‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@
6767
defined(TARGET_CY8CKIT_062S2_43012) || \
6868
defined(TARGET_CY8CKIT_062S2_4343W) || \
6969
defined(TARGET_CY8CKIT_064S2_4343W) || \
70-
defined(TARGET_CYESKIT_064B0S2_4343W) || \
70+
defined(TARGET_CY8CKIT_064B0S2_4343W) || \
7171
defined(TARGET_CY8CPROTO_062_4343W) || \
7272
defined(TARGET_CY8CPROTO_062S2_43012) || \
7373
defined(TARGET_CY8CPROTO_062S3_4343W) || \
@@ -78,9 +78,6 @@
7878
#elif defined(TARGET_CYW9P62S1_43012EVB_01)
7979
#include "S25FS512S_config.h"
8080

81-
#elif defined(TARGET_CY8CPROTO_064_SB)
82-
#include "S25FL128S_config.h"
83-
8481
#endif
8582

8683
#endif // MBED_FLASH_CONFIGS_H

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Wrapper function to initialize all generated code.
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Simple wrapper header containing all generated files.
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,26 @@
1-
/*******************************************************************************
2-
* File Name: cycfg.timestamp
3-
*
4-
* Description:
5-
* Sentinel file for determining if generated source is up to date.
6-
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
9-
*
10-
********************************************************************************
11-
* Copyright 2017-2019 Cypress Semiconductor Corporation
12-
* SPDX-License-Identifier: Apache-2.0
13-
*
14-
* Licensed under the Apache License, Version 2.0 (the "License");
15-
* you may not use this file except in compliance with the License.
16-
* You may obtain a copy of the License at
17-
*
18-
* http://www.apache.org/licenses/LICENSE-2.0
19-
*
20-
* Unless required by applicable law or agreed to in writing, software
21-
* distributed under the License is distributed on an "AS IS" BASIS,
22-
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23-
* See the License for the specific language governing permissions and
24-
* limitations under the License.
25-
********************************************************************************/
26-
1+
/*******************************************************************************
2+
* File Name: cycfg.timestamp
3+
*
4+
* Description:
5+
* Sentinel file for determining if generated source is up to date.
6+
* This file was automatically generated and should not be modified.
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
9+
*
10+
********************************************************************************
11+
* Copyright 2017-2019 Cypress Semiconductor Corporation
12+
* SPDX-License-Identifier: Apache-2.0
13+
*
14+
* Licensed under the Apache License, Version 2.0 (the "License");
15+
* you may not use this file except in compliance with the License.
16+
* You may obtain a copy of the License at
17+
*
18+
* http://www.apache.org/licenses/LICENSE-2.0
19+
*
20+
* Unless required by applicable law or agreed to in writing, software
21+
* distributed under the License is distributed on an "AS IS" BASIS,
22+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23+
* See the License for the specific language governing permissions and
24+
* limitations under the License.
25+
********************************************************************************/
26+

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -27,7 +27,7 @@
2727
#include "cycfg_clocks.h"
2828

2929
#if defined (CY_USING_HAL)
30-
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
30+
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
3131
{
3232
.type = CYHAL_RSC_CLOCK,
3333
.block_num = CYBSP_CSD_CLK_DIV_HW,

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Contains warnings and errors that occurred while generating code for the
66
* design.
77
* This file was automatically generated and should not be modified.
8-
* Device Configurator: 2.0.0.1483
9-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
8+
* cfg-backend-cli: 1.2.0.1483
9+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
1010
*
1111
********************************************************************************
1212
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context =
3434

3535
void init_cycfg_peripherals(void)
3636
{
37-
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
37+
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
3838
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -37,8 +37,8 @@ extern "C" {
3737

3838
#define CYBSP_CSD_ENABLED 1U
3939
#define CY_CAPSENSE_CORE 4u
40-
#define CY_CAPSENSE_CPU_CLK 96000000u
41-
#define CY_CAPSENSE_PERI_CLK 48000000u
40+
#define CY_CAPSENSE_CPU_CLK 100000000u
41+
#define CY_CAPSENSE_PERI_CLK 100000000u
4242
#define CY_CAPSENSE_VDDA_MV 3300u
4343
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
4444
#define CY_CAPSENSE_PERI_DIV_INDEX 0u

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c renamed to ‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
7-
* Device Configurator: 2.0.0.1483
8-
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
7+
* cfg-backend-cli: 1.2.0.1483
8+
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
7474
.channel_num = CYBSP_WCO_OUT_PIN,
7575
};
7676
#endif //defined (CY_USING_HAL)
77-
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
77+
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
7878
{
7979
.outVal = 1,
8080
.driveMode = CY_GPIO_DM_ANALOG,
81-
.hsiom = CYBSP_CSD_TX_HSIOM,
81+
.hsiom = CYBSP_CSD_RX_HSIOM,
8282
.intEdge = CY_GPIO_INTR_DISABLE,
8383
.intMask = 0UL,
8484
.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
9191
.vohSel = 0UL,
9292
};
9393
#if defined (CY_USING_HAL)
94-
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
94+
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
9595
{
9696
.type = CYHAL_RSC_GPIO,
97-
.block_num = CYBSP_CSD_TX_PORT_NUM,
98-
.channel_num = CYBSP_CSD_TX_PIN,
97+
.block_num = CYBSP_CSD_RX_PORT_NUM,
98+
.channel_num = CYBSP_CSD_RX_PIN,
9999
};
100100
#endif //defined (CY_USING_HAL)
101101
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
@@ -425,7 +425,7 @@ void init_cycfg_pins(void)
425425
#endif //defined (CY_USING_HAL)
426426

427427
#if defined (CY_USING_HAL)
428-
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
428+
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
429429
#endif //defined (CY_USING_HAL)
430430

431431
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);

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