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Merge pull request #1305 from bcostm/dev_NUCLEO_F446RE
NUCLEO_F446RE - Improvements + update of all STM32F4 (PWM12 + map/system files)
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‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html

Lines changed: 367 additions & 12 deletions
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‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f401xc.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -665,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
665665
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
666666
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
667667
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
668-
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
669668
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
670669
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
671-
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
672670
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
673-
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
674-
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
671+
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
675672
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
676-
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
673+
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
677674
#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
678675

679676
/* Legacy defines */
@@ -2447,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
24472444
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
24482445
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
24492446
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
2450-
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
24512447
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
24522448
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
24532449

@@ -2643,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
26432639

26442640
/******************** Bits definition for RTC_PRER register *****************/
26452641
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
2646-
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
2642+
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
26472643

26482644
/******************** Bits definition for RTC_WUTR register *****************/
26492645
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
@@ -107,11 +107,11 @@
107107
#endif /* USE_HAL_DRIVER */
108108

109109
/**
110-
* @brief CMSIS Device version number V2.3.0
110+
* @brief CMSIS Device version number V2.3.2
111111
*/
112112
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
113113
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
114-
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
114+
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
115115
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
116116
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
117117
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
88
******************************************************************************
99
* @attention

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f429xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -1060,12 +1060,11 @@ USB_OTG_HostChannelTypeDef;
10601060
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
10611061
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
10621062
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
1063-
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
10641063
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
1065-
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
1066-
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
1064+
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
1065+
#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
10671066
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1068-
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
1067+
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
10691068
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
10701069
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
10711070

@@ -6112,7 +6111,7 @@ USB_OTG_HostChannelTypeDef;
61126111

61136112
/******************** Bits definition for RTC_PRER register *****************/
61146113
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
6115-
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
6114+
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
61166115

61176116
/******************** Bits definition for RTC_WUTR register *****************/
61186117
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
@@ -6517,7 +6516,7 @@ USB_OTG_HostChannelTypeDef;
65176516
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
65186517
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
65196518
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
6520-
#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
6519+
#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
65216520

65226521
/****************** Bit definition for SAI_xCLRFR register ******************/
65236522
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
@@ -107,11 +107,11 @@
107107
#endif /* USE_HAL_DRIVER */
108108

109109
/**
110-
* @brief CMSIS Device version number V2.3.0
110+
* @brief CMSIS Device version number V2.3.2
111111
*/
112112
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
113113
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
114-
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
114+
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
115115
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
116116
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
117117
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
88
******************************************************************************
99
* @attention

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f411xe.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -667,15 +667,12 @@ USB_OTG_HostChannelTypeDef;
667667
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
668668
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
669669
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
670-
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
671670
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
672671
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
673-
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
674672
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
675-
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
676-
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
673+
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
677674
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
678-
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
675+
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
679676
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
680677

681678
/* Legacy defines */
@@ -2456,7 +2453,6 @@ USB_OTG_HostChannelTypeDef;
24562453
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
24572454
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
24582455
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
2459-
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
24602456
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
24612457
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
24622458

@@ -2663,7 +2659,7 @@ USB_OTG_HostChannelTypeDef;
26632659

26642660
/******************** Bits definition for RTC_PRER register *****************/
26652661
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
2666-
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
2662+
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
26672663

26682664
/******************** Bits definition for RTC_WUTR register *****************/
26692665
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
@@ -107,11 +107,11 @@
107107
#endif /* USE_HAL_DRIVER */
108108

109109
/**
110-
* @brief CMSIS Device version number V2.3.0
110+
* @brief CMSIS Device version number V2.3.2
111111
*/
112112
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
113113
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
114-
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
114+
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
115115
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
116116
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
117117
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 02-March-2015
5+
* @version V2.3.2
6+
* @date 26-June-2015
77
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
88
******************************************************************************
99
* @attention

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