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d-katod-kato
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Refactoring PWM driver for RZ/A1
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‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c

Lines changed: 52 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,6 @@ static int32_t period_ch2 = 1;
9090
#endif
9191

9292
#ifdef FUMC_MTU2_PWM
93-
#define MTU2_PWM_SIGNAL 2
94-
9593
typedef enum {
9694
TIOC0A = 0,
9795
TIOC0B,
@@ -111,34 +109,25 @@ typedef enum {
111109
TIOC4D,
112110
} MTU2_PWMType;
113111

114-
static const MTU2_PWMType MTU2_PORT[] = {
115-
TIOC0A, // PWM_TIOC0A
116-
TIOC0C, // PWM_TIOC0C
117-
TIOC1A, // PWM_TIOC1A
118-
TIOC2A, // PWM_TIOC2A
119-
TIOC3A, // PWM_TIOC3A
120-
TIOC3C, // PWM_TIOC3C
121-
TIOC4A, // PWM_TIOC4A
122-
TIOC4C, // PWM_TIOC4C
123-
};
124-
125-
static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = {
126-
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A
127-
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C
128-
{ &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A
129-
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A
130-
{ &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A
131-
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C
132-
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A
133-
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C
134-
};
135-
136-
static __IO uint8_t *TCR_MATCH[] = {
137-
&MTU2TCR_0,
138-
&MTU2TCR_1,
139-
&MTU2TCR_2,
140-
&MTU2TCR_3,
141-
&MTU2TCR_4,
112+
typedef struct {
113+
MTU2_PWMType port;
114+
__IO uint16_t * pulse1;
115+
__IO uint16_t * pulse2;
116+
__IO uint16_t * period1;
117+
__IO uint8_t * tcr;
118+
__IO uint8_t * tmdr;
119+
int max_period;
120+
} st_mtu2_ctrl_t;
121+
122+
static st_mtu2_ctrl_t mtu2_ctl[] = {
123+
{ TIOC0A, &MTU2TGRA_0, &MTU2TGRC_0, &MTU2TGRB_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0A
124+
{ TIOC0C, &MTU2TGRC_0, &MTU2TGRA_0, &MTU2TGRD_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0C
125+
{ TIOC1A, &MTU2TGRA_1, NULL , &MTU2TGRB_1, &MTU2TCR_1, &MTU2TMDR_1, 503000 }, // PWM_TIOC1A
126+
{ TIOC2A, &MTU2TGRA_2, NULL , &MTU2TGRB_2, &MTU2TCR_2, &MTU2TMDR_2, 2000000 }, // PWM_TIOC2A
127+
{ TIOC3A, &MTU2TGRA_3, &MTU2TGRC_3, &MTU2TGRB_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3A
128+
{ TIOC3C, &MTU2TGRC_3, &MTU2TGRA_3, &MTU2TGRD_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3C
129+
{ TIOC4A, &MTU2TGRA_4, &MTU2TGRC_4, &MTU2TGRB_4, &MTU2TCR_4, &MTU2TMDR_4, 2000000 }, // PWM_TIOC4A
130+
{ TIOC4C, &MTU2TGRC_4, &MTU2TGRA_4, &MTU2TGRD_4, &MTU2TCR_4, &MTU2TMDR_4, 2000000 }, // PWM_TIOC4C
142131
};
143132

144133
static __IO uint8_t *TIORH_MATCH[] = {
@@ -157,43 +146,6 @@ static __IO uint8_t *TIORL_MATCH[] = {
157146
&MTU2TIORL_4,
158147
};
159148

160-
static __IO uint16_t *TGRA_MATCH[] = {
161-
&MTU2TGRA_0,
162-
&MTU2TGRA_1,
163-
&MTU2TGRA_2,
164-
&MTU2TGRA_3,
165-
&MTU2TGRA_4,
166-
};
167-
168-
static __IO uint16_t *TGRC_MATCH[] = {
169-
&MTU2TGRC_0,
170-
NULL,
171-
NULL,
172-
&MTU2TGRC_3,
173-
&MTU2TGRC_4,
174-
};
175-
176-
static __IO uint8_t *TMDR_MATCH[] = {
177-
&MTU2TMDR_0,
178-
&MTU2TMDR_1,
179-
&MTU2TMDR_2,
180-
&MTU2TMDR_3,
181-
&MTU2TMDR_4,
182-
};
183-
184-
static int MAX_PERIOD[] = {
185-
125000,
186-
503000,
187-
2000000,
188-
2000000,
189-
2000000,
190-
};
191-
192-
typedef enum {
193-
MTU2_PULSE = 0,
194-
MTU2_PERIOD
195-
} MTU2Signal;
196-
197149
static uint16_t init_mtu2_period_ch[5] = {0};
198150
static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
199151
#endif
@@ -206,26 +158,21 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
206158
if (pwm >= MTU2_PWM_OFFSET) {
207159
#ifdef FUMC_MTU2_PWM
208160
/* PWM by MTU2 */
209-
int tmp_pwm;
210-
211161
// power on
212162
mtu2_init();
213-
163+
214164
obj->pwm = pwm;
215-
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
216-
if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
217-
obj->ch = 4;
165+
st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
166+
167+
obj->ch = (uint8_t)(((uint32_t)p_mtu2_ctl->port & 0x000000F0) >> 4);
168+
if (obj->ch == 4) {
218169
MTU2TOER |= 0x36;
219-
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
220-
obj->ch = 3;
170+
} else if (obj->ch == 3) {
221171
MTU2TOER |= 0x09;
222-
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
223-
obj->ch = 2;
224-
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
225-
obj->ch = 1;
226172
} else {
227-
obj->ch = 0;
173+
// do nothing
228174
}
175+
229176
// Wire pinout
230177
pinmap_pinout(pin, PinMap_PWM);
231178

@@ -284,7 +231,7 @@ void pwmout_write(pwmout_t* obj, float value) {
284231
if (obj->pwm >= MTU2_PWM_OFFSET) {
285232
#ifdef FUMC_MTU2_PWM
286233
/* PWM by MTU2 */
287-
int tmp_pwm;
234+
st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
288235

289236
if (value < 0.0f) {
290237
value = 0.0f;
@@ -293,13 +240,13 @@ void pwmout_write(pwmout_t* obj, float value) {
293240
} else {
294241
// Do Nothing
295242
}
296-
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
297-
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
243+
wk_cycle = (uint32_t)*p_mtu2_ctl->period1;
244+
298245
// set channel match to percentage
299246
if (value == 1.0f) {
300-
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1);
247+
*p_mtu2_ctl->pulse1 = (uint16_t)(wk_cycle - 1);
301248
} else {
302-
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
249+
*p_mtu2_ctl->pulse1 = (uint16_t)((float)wk_cycle * value);
303250
}
304251
#endif
305252
} else {
@@ -336,11 +283,10 @@ float pwmout_read(pwmout_t* obj) {
336283
#ifdef FUMC_MTU2_PWM
337284
/* PWM by MTU2 */
338285
uint32_t wk_pulse;
339-
int tmp_pwm;
340-
341-
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
342-
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
343-
wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
286+
st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
287+
288+
wk_cycle = (uint32_t)*p_mtu2_ctl->period1;
289+
wk_pulse = (uint32_t)*p_mtu2_ctl->pulse1;
344290
value = ((float)wk_pulse / (float)wk_cycle);
345291
#endif
346292
} else {
@@ -403,12 +349,11 @@ void pwmout_period_us(pwmout_t* obj, int us) {
403349
int max_us = 0;
404350

405351
/* PWM by MTU2 */
406-
int tmp_pwm;
352+
st_mtu2_ctrl_t * p_mtu2_ctl = &mtu2_ctl[(int)(obj->pwm - MTU2_PWM_OFFSET)];
407353
uint8_t tmp_tcr_up;
408-
uint8_t tmp_tstr_sp;
409354
uint8_t tmp_tstr_st;
410-
411-
max_us = MAX_PERIOD[obj->ch];
355+
356+
max_us = p_mtu2_ctl->max_period;
412357
if (us > max_us) {
413358
us = max_us;
414359
} else if (us < 1) {
@@ -436,37 +381,34 @@ void pwmout_period_us(pwmout_t* obj, int us) {
436381
}
437382
wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
438383

439-
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
440-
if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
384+
if (((uint8_t)p_mtu2_ctl->port & 0x0F) == 0x02) {
441385
tmp_tcr_up = 0xC0;
442386
} else {
443387
tmp_tcr_up = 0x40;
444388
}
445389
if ((obj->ch == 4) || (obj->ch == 3)) {
446-
tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
447390
tmp_tstr_st = (1 << (obj->ch + 3));
448391
} else {
449-
tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
450392
tmp_tstr_st = (1 << obj->ch);
451393
}
394+
452395
// Counter Stop
453-
MTU2TSTR &= tmp_tstr_sp;
454-
wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
455-
*TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
396+
MTU2TSTR &= ~tmp_tstr_st;
397+
wk_last_cycle = *p_mtu2_ctl->period1;
398+
*p_mtu2_ctl->tcr = tmp_tcr_up | wk_cks;
456399
*TIORH_MATCH[obj->ch] = 0x21;
457400
if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
458401
*TIORL_MATCH[obj->ch] = 0x21;
459402
}
460-
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
461-
462-
// Set duty again(TGRA)
463-
set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
464-
if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
465-
// Set duty again(TGRC)
466-
set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
403+
// Set period
404+
*p_mtu2_ctl->period1 = (uint16_t)wk_cycle;
405+
// Set duty again
406+
set_mtu2_duty_again(p_mtu2_ctl->pulse1, wk_last_cycle, wk_cycle);
407+
if (p_mtu2_ctl->pulse2 != NULL) {
408+
set_mtu2_duty_again(p_mtu2_ctl->pulse2, wk_last_cycle, wk_cycle);
467409
}
468-
*TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
469-
410+
// Set mode
411+
*p_mtu2_ctl->tmdr = 0x02; // PWM mode 1
470412
// Counter Start
471413
MTU2TSTR |= tmp_tstr_st;
472414
// Save for future use

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