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maciejbocianski0xc0170
maciejbocianski
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0xc0170
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hal-qspi test: code refactoring
1 parent 378f37a commit 72227e2

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3 files changed

+46
-41
lines changed

3 files changed

+46
-41
lines changed

‎TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,15 @@
108108

109109

110110
// single quad enable flag for both dual and quad mode
111-
#define QUAD_ENABLE_IMPLEMENTATION() \
111+
#define QUAD_ENABLE() \
112112
\
113113
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
114114
\
115+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
116+
return QSPI_STATUS_ERROR; \
117+
} \
118+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
119+
\
115120
reg_data[0] = STATUS_BIT_QE; \
116121
qspi.cmd.build(QSPI_CMD_WRSR); \
117122
\
@@ -132,10 +137,15 @@
132137

133138

134139

135-
#define QUAD_DISABLE_IMPLEMENTATION() \
140+
#define QUAD_DISABLE() \
136141
\
137142
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
138143
\
144+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
145+
return QSPI_STATUS_ERROR; \
146+
} \
147+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
148+
\
139149
reg_data[0] = 0; \
140150
qspi.cmd.build(QSPI_CMD_WRSR); \
141151
\
@@ -156,7 +166,7 @@
156166

157167

158168

159-
#define FAST_MODE_ENABLE_IMPLEMENTATION() \
169+
#define FAST_MODE_ENABLE() \
160170
\
161171
qspi_status_t ret; \
162172
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \

‎TESTS/mbed_hal/qspi/main.cpp

Lines changed: 19 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -71,11 +71,11 @@ uint8_t rx_buf[DATA_SIZE_1024];
7171

7272
static void log_data(const char *str, uint8_t *data, uint32_t size)
7373
{
74-
printf("%s: ", str);
74+
utest_printf("%s: ", str);
7575
for (uint32_t j = 0; j < size; j++) {
76-
printf("%02X ", data[j]);
76+
utest_printf("%02X ", data[j]);
7777
}
78-
printf("\r\n");
78+
utest_printf("\r\n");
7979
}
8080

8181

@@ -171,19 +171,19 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
171171
if (tx_buf[i] != rx_buf[i]) {
172172
log_data("tx data", tx_buf, data_size);
173173
log_data("rx data", rx_buf, data_size);
174-
printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
174+
utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
175175
TEST_ASSERT_EQUAL(tx_buf[i], rx_buf[i]);
176176
}
177177
}
178178

179179
#ifdef QSPI_TEST_LOG_FLASH_TIME
180-
printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
180+
utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
181181
#endif
182182

183183
#ifdef QSPI_TEST_LOG_DATA
184184
log_data("tx data", tx_buf, data_size);
185185
log_data("rx data", rx_buf, data_size);
186-
printf("rx/tx data match\r\n");
186+
utest_printf("rx/tx data match\r\n");
187187
#endif
188188
}
189189
}
@@ -222,19 +222,13 @@ void qspi_write_read_test(void)
222222

223223
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
224224
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
225-
ret = write_enable(qspi);
226-
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
227-
WAIT_FOR(WRSR_MAX_TIME, qspi);
228225
ret = dual_enable(qspi);
229226
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
230227
WAIT_FOR(WRSR_MAX_TIME, qspi);
231228
}
232229

233230
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
234231
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
235-
ret = write_enable(qspi);
236-
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
237-
WAIT_FOR(WRSR_MAX_TIME, qspi);
238232
ret = quad_enable(qspi);
239233
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
240234
WAIT_FOR(WRSR_MAX_TIME, qspi);
@@ -248,10 +242,13 @@ void qspi_write_read_test(void)
248242
WAIT_FOR(WRSR_MAX_TIME, qspi);
249243

250244
#ifdef QSPI_TEST_LOG_FLASH_STATUS
251-
printf("Status "); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
252-
printf("Config 0 "); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
245+
utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
246+
utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
253247
#ifdef CONFIG_REG1
254-
printf("Config 1 "); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
248+
utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
249+
#endif
250+
#ifdef CONFIG_REG2
251+
utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi);
255252
#endif
256253
#endif
257254

@@ -265,19 +262,13 @@ void qspi_write_read_test(void)
265262

266263
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
267264
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
268-
ret = write_enable(qspi);
269-
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
270-
WAIT_FOR(WRSR_MAX_TIME, qspi);
271265
ret = dual_disable(qspi);
272266
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
273267
WAIT_FOR(WRSR_MAX_TIME, qspi);
274268
}
275269

276270
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
277271
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
278-
ret = write_enable(qspi);
279-
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
280-
WAIT_FOR(WRSR_MAX_TIME, qspi);
281272
ret = quad_disable(qspi);
282273
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
283274
WAIT_FOR(WRSR_MAX_TIME, qspi);
@@ -321,10 +312,13 @@ void qspi_init_free_test(void)
321312
flash_init(qspi);
322313

323314
#ifdef QSPI_TEST_LOG_FLASH_STATUS
324-
printf("Status "); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
325-
printf("Config 0 "); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
315+
utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
316+
utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
326317
#ifdef CONFIG_REG1
327-
printf("Config 1 "); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
318+
utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
319+
#endif
320+
#ifdef CONFIG_REG2
321+
utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi);
328322
#endif
329323
#endif
330324

@@ -375,7 +369,7 @@ void qspi_frequency_test(void)
375369

376370
void qspi_memory_id_test()
377371
{
378-
printf("*** %s memory config loaded ***\r\n", QSPI_FLASH_CHIP_STRING);
372+
utest_printf("*** %s memory config loaded ***\r\n", QSPI_FLASH_CHIP_STRING);
379373
}
380374

381375

‎TESTS/mbed_hal/qspi/qspi_test_utils.cpp

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
* limitations under the License.
1515
*/
1616

17+
#include "utest/utest.h"
1718

1819
#include "hal/qspi_api.h"
1920
#include "qspi_test_utils.h"
@@ -166,12 +167,12 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi)
166167
ret = read_register(cmd, reg, reg_size, qspi);
167168
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
168169

169-
for (int j = 0; j < reg_size; j++) {
170-
printf("register byte %d data: ", j);
170+
for (uint32_t j = 0; j < reg_size; j++) {
171+
utest_printf("register byte %u data: ", j);
171172
for(int i = 0; i < 8; i++) {
172-
printf("%s ", ((reg[j] & (1 << i)) & 0xFF) == 0 ? "0" : "1");
173+
utest_printf("%s ", ((reg[j] & (1 << i)) & 0xFF) == 0 ? "0" : "1");
173174
}
174-
printf("\r\n");
175+
utest_printf("\r\n");
175176
}
176177
}
177178

@@ -183,36 +184,36 @@ qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi)
183184

184185
qspi_status_t dual_enable(Qspi &qspi)
185186
{
186-
#ifdef DUAL_ENABLE_IMPLEMENTATION
187-
DUAL_ENABLE_IMPLEMENTATION();
187+
#ifdef DUAL_ENABLE
188+
DUAL_ENABLE();
188189
#else
189-
QUAD_ENABLE_IMPLEMENTATION();
190+
QUAD_ENABLE();
190191
#endif
191192
}
192193

193194
qspi_status_t dual_disable(Qspi &qspi)
194195
{
195-
#ifdef DUAL_DISABLE_IMPLEMENTATION
196-
DUAL_DISABLE_IMPLEMENTATION();
196+
#ifdef DUAL_DISABLE
197+
DUAL_DISABLE();
197198
#else
198-
QUAD_DISABLE_IMPLEMENTATION();
199+
QUAD_DISABLE();
199200
#endif
200201

201202
}
202203

203204
qspi_status_t quad_enable(Qspi &qspi)
204205
{
205-
QUAD_ENABLE_IMPLEMENTATION();
206+
QUAD_ENABLE();
206207
}
207208

208209
qspi_status_t quad_disable(Qspi &qspi)
209210
{
210-
QUAD_DISABLE_IMPLEMENTATION();
211+
QUAD_DISABLE();
211212
}
212213

213214
qspi_status_t fast_mode_enable(Qspi &qspi)
214215
{
215-
FAST_MODE_ENABLE_IMPLEMENTATION();
216+
FAST_MODE_ENABLE();
216217
}
217218

218219
bool is_dual_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)

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