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Merge pull request #11770 from morser499/pr/cm0-images
Update CM0P pre-built images to build 1.0.0.35
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‎targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/README.md

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# PSoC 6 Cortex M0+ BLESS Controller pre-built image (CM0P_BLESS)
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### Overview
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Pre-compiled BLESS Controller image executed on the Cortex M0+ core of the PSoC 6 dual-core MCU.
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The image is provided as C array ready to be compiled as part of the Cortex M4 application.
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The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script.
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This image is used only in BLE dual CPU mode. In this mode, the BLE functionality is split between
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CM0+ (controller) and CM4 (host). It uses IPC for communication between two CPU cores where both the
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controller and host run:
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------------------------------- ------------------------------------
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| CM0p (pre-built image) | | CM4 |
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| -------------------- ----- | | ----- ------------------------ |
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| | | | H | | IPC | | | | BLE Application | |
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| | BLE Controller |--| c | |<-------->| | | ------------------------ |
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| | (LL) | | I | |(commands,| | | | | |
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| | | ----- | events) | | | ----------------- | |
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| -------------------- | | | H | | BLE Profiles | | |
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------------------------------- | | C | ----------------- | |
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| | | I | | | |
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------------------------ | | | ------------------------- |
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| BLE HW | | | |--| BLE Host (GAP, L2CAP,| |
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------------------------ | | | | SM, ATT) | |
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| | | ------------------------- |
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| ----- |
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------------------------------------
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BLESS Controller pre-built image executes the following steps:
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- configures BLESS interrupt
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- registers IPC-pipe callback for BLE middleware; the BLE middleware uses this callback to
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initialize and enable the BLE controller when BLE middleware operates in BLE dual CPU mode
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- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000
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- goes to the while loop where processes BLE controller events and puts the CM0+ core into Deep Sleep.
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### Usage
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To use this image, update the ram, flash, and FLASH_CM0P_SIZE values in the linker script for CM4:
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```
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Example for the GCC compiler:
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...
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MEMORY
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{
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...
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ram (rwx) : ORIGIN = 0x08003000, LENGTH = 0x044800
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flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
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...
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}
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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FLASH_CM0P_SIZE = 0x20000;
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...
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```
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```
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Example for the IAR compiler:
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...
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/* RAM */
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define symbol __ICFEDIT_region_IRAM1_start__ = 0x08003000;
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define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
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/* Flash */
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define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
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define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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define symbol FLASH_CM0P_SIZE = 0x20000;
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...
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```
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```
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Example for ARMC6 compiler:
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...
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; RAM
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#define RAM_START 0x08003000
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#define RAM_SIZE 0x00044800
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; Flash
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#define FLASH_START 0x10000000
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#define FLASH_SIZE 0x00100000
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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#define FLASH_CM0P_SIZE 0x20000
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...
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```
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To use this image in the custom BSP, adjust the BSP target makefile to
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add the COMPONENT_CM0P_BLESS directory to the list of components
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discovered by ModusToolbox build system:
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```
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COMPONENTS+=CM0P_BLESS
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```
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Make sure there is a single CM0P_* component included in the COMPONENTS list
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(it might be needed to remove CM0P_SLEEP from the list of standard BSP components).
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---
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Copyright (c) Cypress Semiconductor Corporation, 2019.

‎targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c

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‎targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/README.md

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# PSoC 6 Cortex M0+ Crypto server prebuilt image (CM0P_CRYPTO)
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### Overview
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Crypto server prebuilt application image is executed on the Cortex M0+ core of the PSoC 6 dual-core MCU.
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The image is provided as C array ready to be compiled as part of the Cortex M4 application.
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The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script.
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The Crypto server image executes the following steps:
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- configures IPC channel for data exchange between client and server applications;
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- configures three interrupts: an IPC notify interrupt, an IPC release interrupt, and an interrupt for error handling.
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- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10008000
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- goes to the infinite loop that processes the crypto server events and puts the CM0+ core into Deep Sleep.
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### Usage
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To use this image, update the FLASH_CM0P_SIZE value in the linker script for CM4:
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```
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Example for the GCC compiler:
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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FLASH_CM0P_SIZE = 0x8000;
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...
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```
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```
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Example for the IAR compiler:
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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define symbol FLASH_CM0P_SIZE = 0x8000;
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...
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```
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```
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Example for ARMC6 compiler:
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...
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/* The size and start addresses of the Cortex-M0+ application image */
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#define FLASH_CM0P_SIZE 0x8000
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...
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```
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To use this image in the custom BSP, adjust the BSP target makefile to
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add the COMPONENT_CM0P_CRYPTO directory to the list of components
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discovered by ModusToolbox build system:
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```
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COMPONENTS+=CM0P_CRYPTO
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```
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Make sure there is a single CM0P_* component included in the COMPONENTS list
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(it might be needed to remove CM0P_SLEEP from the list of standard BSP components).
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### Crypto client configuration
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Example configuration of the crypto client for the Cortex-M4 core
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compatible with the prebuilt crypto server CM0+ application:
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```
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#define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */
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#define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */
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#define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */
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#define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */
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#define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */
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#define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */
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const cy_stc_crypto_config_t myCryptoConfig =
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{
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/* .ipcChannel */ MY_CHAN_CRYPTO,
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/* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV,
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/* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI,
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/* .releaseNotifierConfig */ {
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/* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
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/* .intrPriority */ 2u,
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},
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/* .userCompleteCallback */ NULL,
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/* .userGetDataHandler */ NULL,
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/* .userErrorHandler */ NULL,
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/* .acquireNotifierConfig */ {
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/* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
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/* .intrPriority */ 2u,
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},
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/* .cryptoErrorIntrConfig */ {
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/* .cm0pSrc */ cpuss_interrupt_crypto_IRQn,
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/* .intrPriority */ 2u,
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}
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};
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```
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Refer to the [PDL API Reference Guide][pdl_crypto] for more information related to the PSoC 6 Crypto client configuration.
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---
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Copyright (c) Cypress Semiconductor Corporation, 2019.
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[pdl_crypto]: https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__crypto__cli__srv.html

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