@@ -394,7 +394,7 @@ int OSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
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_mutex.lock ();
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if (size % 2 != 0 ) {
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- size ++;
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+ size ++;
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}
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if (OSPI_STATUS_OK != _ospi_send_read_command (_read_instruction, buffer, addr, size)) {
@@ -501,7 +501,7 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size)
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region,
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_sfdp_info.smptbl );
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// cur_erase_inst should be 4-Byte erase instruction for Macronix octa flash OPI mode
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- cur_erase_inst = (_address_size == OSPI_CFG_ADDR_SIZE_32 ) ? _sfdp_info.fbatbl .erase_type_4_byte_inst_arr [type] : _sfdp_info.smptbl .erase_type_inst_arr [type];
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+ cur_erase_inst = (_address_size == OSPI_CFG_ADDR_SIZE_32) ? _sfdp_info.fbatbl .erase_type_4_byte_inst_arr [type] : _sfdp_info.smptbl .erase_type_inst_arr [type];
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eu_size = _sfdp_info.smptbl .erase_type_size_arr [type];
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} else {
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// Must use legacy 4k erase instruction
@@ -634,9 +634,8 @@ int OSPIFBlockDevice::change_mode(int mode)
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char config_reg2 = 0 ;
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if (((mode == SPI) && (_read_instruction == OSPIF_INST_READ_4B)) ||
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- ((mode == SOPI) && (_read_instruction == DTROSPIF_INST_READ_OCTA_STR)) ||
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- ((mode == DOPI) && (_read_instruction == DTROSPIF_INST_READ_OCTA_DTR))) {
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-
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+ ((mode == SOPI) && (_read_instruction == DTROSPIF_INST_READ_OCTA_STR)) ||
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+ ((mode == DOPI) && (_read_instruction == DTROSPIF_INST_READ_OCTA_DTR))) {
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tr_debug (" Flash does not need change mode" );
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}
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@@ -665,7 +664,7 @@ int OSPIFBlockDevice::change_mode(int mode)
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_ospi.configure_format (OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32,
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OSPI_CFG_BUS_SINGLE, 0 , OSPI_CFG_BUS_SINGLE, 0 );
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- // Write new Status Register Setup
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+ // Write new Status Register Setup
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if (_set_write_enable () != 0 ) {
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tr_error (" Write Enabe failed" );
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return -1 ;
@@ -692,10 +691,9 @@ int OSPIFBlockDevice::change_mode(int mode)
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_ospi.configure_format (_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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0 , _data_width, 0 );
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- }
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- else if (mode == DOPI) {
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+ } else if (mode == DOPI) {
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if ((_read_instruction != OSPIF_INST_READ_4B) && (_read_instruction != OSPIF_INST_READ_DEFAULT)) {// chang mode from SOPI to SPI
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- // Write new Status Register Setup
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+ // Write new Status Register Setup
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if (_set_write_enable () != 0 ) {
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tr_error (" Write Enabe failed" );
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return -1 ;
@@ -718,7 +716,7 @@ int OSPIFBlockDevice::change_mode(int mode)
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_ospi.configure_format (OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32,
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OSPI_CFG_BUS_SINGLE, 0 , OSPI_CFG_BUS_SINGLE, 0 );
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- // Write new Status Register Setup
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+ // Write new Status Register Setup
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if (_set_write_enable () != 0 ) {
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tr_error (" Write Enabe failed" );
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return -1 ;
@@ -745,9 +743,8 @@ int OSPIFBlockDevice::change_mode(int mode)
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_ospi.configure_format (_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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0 , _data_width, 0 );
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- }
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- else if (mode == SPI) {
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- // Write new Status Register Setup
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+ } else if (mode == SPI) {
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+ // Write new Status Register Setup
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if (_set_write_enable () != 0 ) {
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tr_error (" Write Enabe failed" );
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return -1 ;
@@ -1070,7 +1067,7 @@ int OSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
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// read_inst = basic_param_table_ptr[OSPIF_BASIC_PARAM_TABLE_888_READ_INST_BYTE];
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is_opi_mode = true ;
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_dummy_cycles = (basic_param_table_ptr[OSPIF_BASIC_PARAM_TABLE_888_READ_INST_BYTE - 1 ] >> 5 )
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- + (basic_param_table_ptr[OSPIF_BASIC_PARAM_TABLE_888_READ_INST_BYTE - 1 ] & 0x1F );
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+ + (basic_param_table_ptr[OSPIF_BASIC_PARAM_TABLE_888_READ_INST_BYTE - 1 ] & 0x1F );
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tr_debug (" Read Bus Mode set to 8-8-8, Instruction: 0x%xh" , _read_instruction);
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// _inst_width = OSPI_CFG_BUS_OCTA;
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// _inst_size = OSPI_CFG_INST_SIZE_16;
@@ -1239,7 +1236,7 @@ int OSPIFBlockDevice::_sfdp_detect_and_enable_4byte_addressing(uint8_t *basic_pa
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switch (_read_instruction) {
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case OSPIF_INST_READ_DEFAULT:
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_read_instruction = OSPIF_INST_READ_4B;
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- break ;
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+ break ;
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case 0xc2 :
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break ;
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}
@@ -1321,7 +1318,7 @@ int OSPIFBlockDevice::_sfdp_parse_4_byte_inst_table(Callback<int(bd_addr_t, void
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for (int i_ind = 0 ; i_ind < 4 ; i_ind++) {
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sfdp_info.fbatbl .erase_type_4_byte_inst_arr [i_ind] = OSPI_NO_INST; // Default for unsupported type
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if (four_byte_inst_table[OSPIF_4_BYTE_INST_TABLE_ERASE_SUPPORT_BYTE] & (FOURBYTE_INST_ERASE_TYPE_1_BITMASK << i_ind)) {
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- sfdp_info.fbatbl .erase_type_4_byte_inst_arr [i_ind] = four_byte_inst_table[OSPIF_4_BYTE_INST_TABLE_INST_ERASE_TYPE_1_BYTE + i_ind];
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+ sfdp_info.fbatbl .erase_type_4_byte_inst_arr [i_ind] = four_byte_inst_table[OSPIF_4_BYTE_INST_TABLE_INST_ERASE_TYPE_1_BYTE + i_ind];
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}
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tr_debug (" Erase Type %d - Inst: 0x%xh" , (i_ind + 1 ), sfdp_info.fbatbl .erase_type_4_byte_inst_arr [i_ind]);
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}
@@ -1739,14 +1736,13 @@ ospi_status_t OSPIFBlockDevice::_ospi_send_general_command(ospi_inst_t instructi
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return status;
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}
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- if ((_inst_width == OSPI_CFG_BUS_OCTA ) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR )){
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+ if ((_inst_width == OSPI_CFG_BUS_OCTA) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR)){
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if ((instruction == OSPIF_INST_RSR1) || (instruction == OSPIF_INST_RDID) ||
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- (instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR)) {
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- _ospi.configure_format (_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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+ (instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR)) {
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+ _ospi.configure_format (_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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0 , _data_width, 4 );
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addr = 0 ;
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- }
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- else if ((instruction == OSPIF_INST_WSR1) ) {
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+ } else if ((instruction == OSPIF_INST_WSR1)) {
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addr = 0 ;
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}
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}
@@ -1758,9 +1754,9 @@ ospi_status_t OSPIFBlockDevice::_ospi_send_general_command(ospi_inst_t instructi
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return status;
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}
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- if (((_inst_width == OSPI_CFG_BUS_OCTA) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR )) &&
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- ((instruction == OSPIF_INST_RSR1) || (instruction == OSPIF_INST_RDID) ||
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- (instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR))) {
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+ if (((_inst_width == OSPI_CFG_BUS_OCTA) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR)) &&
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+ ((instruction == OSPIF_INST_RSR1) || (instruction == OSPIF_INST_RDID) ||
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+ (instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR))) {
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_ospi.configure_format (_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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0 , _data_width, 0 );
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}
@@ -1775,16 +1771,17 @@ int OSPIFBlockDevice::_ospi_send_read_sfdp_command(bd_addr_t addr, void *rx_buff
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if (_need_define_sfdp_para) {
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if (addr < 30 ) {
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- for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++)
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+ for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++) {
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* (rx_buffer_tmp+ i_ind)= _sfdp_head_table[i_ind+addr];
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- }
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- else if (addr == 0x30 ) {
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- for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++)
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+ }
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+ } else if (addr == 0x30 ) {
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+ for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++) {
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*(rx_buffer_tmp+ i_ind) = _sfdp_basic_param_table[i_ind];
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- }
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- else if (addr == 0xc0 ) {
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- for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++)
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+ }
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+ } else if (addr == 0xc0 ) {
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+ for (uint8_t i_ind = 0 ; i_ind < rx_len; i_ind++) {
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*(rx_buffer_tmp+ i_ind) = _sfdp_4_byte_inst_table[i_ind];
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+ }
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}
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} else {
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// SFDP read instruction requires 1-1-1 bus mode with 8 dummy cycles and a 3-byte address
@@ -1860,7 +1857,7 @@ ospi_status_t OSPIFBlockDevice::_ospi_write_status_registers(uint8_t *reg_buffer
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status = _ospi_send_general_command (OSPIF_INST_WSR1, OSPI_NO_ADDRESS_COMMAND,
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(char *) reg_buffer, 1 ,
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NULL , 0 );
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- // for octa flash DOPI mode, WRSR just write 1 byte, but the byte number need to even because of protocol
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+ // for octa flash DOPI mode, WRSR just write 1 byte, but the byte number need to even because of protocol
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} else if (_read_instruction == DTROSPIF_INST_READ_OCTA_DTR) {
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status = _ospi_send_general_command (OSPIF_INST_WSR1, OSPI_NO_ADDRESS_COMMAND,
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(char *) reg_buffer, 2 ,
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