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[HAL LPC408x] Fix mask bits for SPI clock rate
1 parent cb9b2b0 commit 72e8241

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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
118118

119119
int FRF = 0; // FRF (frame format) = SPI
120120
uint32_t tmp = obj->spi->CR0;
121-
tmp &= ~(0xFFFF);
121+
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
122122
tmp |= DSS << 0
123123
| FRF << 4
124124
| SPO << 6
@@ -153,7 +153,7 @@ void spi_frequency(spi_t *obj, int hz) {
153153
obj->spi->CPSR = prescaler;
154154

155155
// divider
156-
obj->spi->CR0 &= ~(0xFFFF << 8);
156+
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
157157
obj->spi->CR0 |= (divider - 1) << 8;
158158
ssp_enable(obj);
159159
return;

targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
9898

9999
int FRF = 0; // FRF (frame format) = SPI
100100
uint32_t tmp = obj->spi->CR0;
101-
tmp &= ~(0xFFFF);
101+
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
102102
tmp |= DSS << 0
103103
| FRF << 4
104104
| SPO << 6
@@ -133,7 +133,7 @@ void spi_frequency(spi_t *obj, int hz) {
133133
obj->spi->CPSR = prescaler;
134134

135135
// divider
136-
obj->spi->CR0 &= ~(0xFFFF << 8);
136+
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
137137
obj->spi->CR0 |= (divider - 1) << 8;
138138
ssp_enable(obj);
139139
return;

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