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STM32L476: no HSE is present in NUCLEO and DISCO boards
1 parent c57427f commit 757944e

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2 files changed

+33
-25
lines changed

2 files changed

+33
-25
lines changed

targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/system_stm32l4xx.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
*/
132132

133133
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
134-
#define USE_PLL_HSE_EXTC (1) // Use external clock
134+
#define USE_PLL_HSE_EXTC (0) // Use external clock
135135
#define USE_PLL_HSE_XTAL (0) // Use external xtal
136136
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
137137
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
@@ -547,7 +547,7 @@ uint8_t SetSysClock_PLL_MSI(void)
547547
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
548548
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
549549

550-
RCC_OscInitStruct.HSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
550+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
551551
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
552552
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
553553
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
@@ -568,10 +568,10 @@ uint8_t SetSysClock_PLL_MSI(void)
568568
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
569569
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
570570
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
571-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
572-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
573-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
574-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 80 MHz
571+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
572+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
573+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
574+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
575575
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
576576
{
577577
return 0; // FAIL

targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.c

Lines changed: 27 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
*/
132132

133133
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
134-
#define USE_PLL_HSE_EXTC (1) // Use external clock
134+
#define USE_PLL_HSE_EXTC (0) // Use external clock
135135
#define USE_PLL_HSE_XTAL (0) // Use external xtal
136136
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
137137
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
@@ -530,40 +530,48 @@ uint8_t SetSysClock_PLL_MSI(void)
530530
{
531531
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
532532
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
533-
533+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
534+
534535
// Enable LSE Oscillator to automatically calibrate the MSI clock
535536
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
536537
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
537538
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
538539
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
539540
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
540541
}
541-
542-
// Enable MSI oscillator and activate PLL with MSI as source
543-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
542+
543+
HAL_RCCEx_DisableLSECSS();
544+
/* Enable MSI Oscillator and activate PLL with MSI as source */
545+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
544546
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
545547
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
546548
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
547-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
548-
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
549-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
550-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
551-
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
552-
RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
553-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
554-
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
555-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
549+
550+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
551+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
552+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
553+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
554+
RCC_OscInitStruct.PLL.PLLM = 6;
555+
RCC_OscInitStruct.PLL.PLLN = 40;
556+
RCC_OscInitStruct.PLL.PLLP = 7;
557+
RCC_OscInitStruct.PLL.PLLQ = 4;
558+
RCC_OscInitStruct.PLL.PLLR = 4;
556559
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
557560
{
558561
return 0; // FAIL
559562
}
560-
563+
/* Enable MSI Auto-calibration through LSE */
564+
HAL_RCCEx_EnableMSIPLLMode();
565+
/* Select MSI output as USB clock source */
566+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
567+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
568+
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
561569
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
562570
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
563-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
564-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
565-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
566-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
571+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
572+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
573+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
574+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
567575
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
568576
{
569577
return 0; // FAIL

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