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LPTMR timer - OSCEN set, GCC startup vectors add
1 parent b73b57d commit 78140c4

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7 files changed

+72
-62
lines changed

7 files changed

+72
-62
lines changed

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/MK20D5.sct

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
55
*(InRoot$$Sections)
66
.ANY (+RO)
77
}
8-
; 8_byte_aligned(61 vect * 4 bytes) = 8_byte_aligned(0xF4) = 0xF8
8+
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
99
; 0x4000 - 0xF8 = 0x3F08
1010
RW_IRAM1 0x1FFFE0F8 0x3F08 {
1111
.ANY (+RW +ZI)

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s

Lines changed: 46 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -86,39 +86,52 @@ __isr_vector:
8686
.long SysTick_Handler /* SysTick Handler */
8787

8888
/* External interrupts */
89-
.long WDT_IRQHandler /* 0: Watchdog Timer */
90-
.long RTC_IRQHandler /* 1: Real Time Clock */
91-
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
92-
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
93-
.long MCIA_IRQHandler /* 4: MCIa */
94-
.long MCIB_IRQHandler /* 5: MCIb */
95-
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
96-
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
97-
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
98-
.long UART4_IRQHandler /* 9: UART4 - not connected */
99-
.long AACI_IRQHandler /* 10: AACI / AC97 */
100-
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
101-
.long ENET_IRQHandler /* 12: Ethernet */
102-
.long USBDC_IRQHandler /* 13: USB Device */
103-
.long USBHC_IRQHandler /* 14: USB Host Controller */
104-
.long CHLCD_IRQHandler /* 15: Character LCD */
105-
.long FLEXRAY_IRQHandler /* 16: Flexray */
106-
.long CAN_IRQHandler /* 17: CAN */
107-
.long LIN_IRQHandler /* 18: LIN */
108-
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
109-
.long 0 /* 20: Reserved */
110-
.long 0 /* 21: Reserved */
111-
.long 0 /* 22: Reserved */
112-
.long 0 /* 23: Reserved */
113-
.long 0 /* 24: Reserved */
114-
.long 0 /* 25: Reserved */
115-
.long 0 /* 26: Reserved */
116-
.long 0 /* 27: Reserved */
117-
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
118-
.long 0 /* 29: Reserved - CPU FPGA */
119-
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
120-
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
121-
89+
.long DMA0_IRQHandler /* 0: Watchdog Timer */
90+
.long DMA1_IRQHandler /* 1: Real Time Clock */
91+
.long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
92+
.long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
93+
.long DMA_Error_IRQHandler /* 4: MCIa */
94+
.long 0 /* 5: MCIb */
95+
.long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
96+
.long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
97+
.long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
98+
.long LLW_IRQHandler /* 9: UART4 - not connected */
99+
.long Watchdog_IRQHandler /* 10: AACI / AC97 */
100+
.long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
101+
.long SPI0_IRQHandler /* 12: Ethernet */
102+
.long I2S0_Tx_IRQHandler /* 13: USB Device */
103+
.long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
104+
.long UART0_LON_IRQHandler /* 15: Character LCD */
105+
.long UART0_RX_TX_IRQHandler /* 16: Flexray */
106+
.long UART0_ERR_IRQHandler /* 17: CAN */
107+
.long UART1_RX_TX_IRQHandler /* 18: LIN */
108+
.long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
109+
.long UART2_RX_TX_IRQHandler /* 20: Reserved */
110+
.long UART2_ERR_IRQHandler /* 21: Reserved */
111+
.long ADC0_IRQHandler /* 22: Reserved */
112+
.long CMP0_IRQHandler /* 23: Reserved */
113+
.long CMP1_IRQHandler /* 24: Reserved */
114+
.long FTM0_IRQHandler /* 25: Reserved */
115+
.long FTM1_IRQHandler /* 26: Reserved */
116+
.long CMT_IRQHandler /* 27: Reserved */
117+
.long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
118+
.long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
119+
.long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
120+
.long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
121+
.long PIT2_IRQHandler
122+
.long PIT3_IRQHandler
123+
.long PDB0_IRQHandler
124+
.long USB0_IRQHandler
125+
.long USBDCD_IRQHandler
126+
.long TSI0_IRQHandler
127+
.long MCG_IRQHandler
128+
.long LPTimer_IRQHandler
129+
.long PORTA_IRQHandler
130+
.long PORTB_IRQHandler
131+
.long PORTC_IRQHandler
132+
.long PORTD_IRQHandler
133+
.long PORTE_IRQHandler
134+
.long SWI_IRQHandler
122135
.size __isr_vector, . - __isr_vector
123136

124137
.text

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,12 @@
22
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
33
*
44
* CMSIS-style functionality to support dynamic vectors
5-
*/
5+
*/
66

77
#ifndef MBED_CMSIS_NVIC_H
88
#define MBED_CMSIS_NVIC_H
99

10-
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
10+
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
1111
#define NVIC_USER_IRQ_OFFSET 16
1212

1313
#include "cmsis.h"

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/analogin_api.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,8 @@ static const PinMap PinMap_ADC[] = {
3535

3636
void analogin_init(analogin_t *obj, PinName pin) {
3737
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
38-
if (obj->adc == (ADCName)NC) {
38+
if (obj->adc == (ADCName)NC)
3939
error("ADC pin mapping failed");
40-
}
4140

4241
SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
4342

@@ -72,7 +71,6 @@ uint16_t analogin_read_u16(analogin_t *obj) {
7271
// Wait Conversion Complete
7372
while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
7473

75-
// Return value
7674
return (uint16_t)ADC0->R[0];
7775
}
7876

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/gpio_irq_api.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@ static void handle_interrupt_in(PORT_Type *port, int ch_base) {
3737
if (port->ISFR & pmask) {
3838
mask |= pmask;
3939
uint32_t id = channel_ids[ch_base + i];
40-
if (id == 0) continue;
40+
if (id == 0)
41+
continue;
4142

4243
GPIO_Type *gpio = PTA;
4344
gpio_irq_event event = IRQ_NONE;
@@ -70,7 +71,8 @@ void gpio_irqD(void) {handle_interrupt_in(PORTD, 96);}
7071
void gpio_irqE(void) {handle_interrupt_in(PORTE, 128);}
7172

7273
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
73-
if (pin == NC) return -1;
74+
if (pin == NC)
75+
return -1;
7476

7577
irq_handler = handler;
7678

@@ -129,9 +131,8 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
129131

130132
switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
131133
case IRQ_DISABLED:
132-
if (enable) {
134+
if (enable)
133135
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
134-
}
135136
break;
136137

137138
case IRQ_RAISING_EDGE:

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/i2c_api.c

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -79,12 +79,11 @@ int i2c_start(i2c_t *obj) {
7979
// if we are in the middle of a transaction
8080
// activate the repeat_start flag
8181
if (obj->i2c->S & I2C_S_BUSY_MASK) {
82-
// KL25Z errata sheet: repeat start cannot be generated if the
83-
// I2Cx_F[MULT] field is set to a non-zero value
8482
temp = obj->i2c->F >> 6;
8583
obj->i2c->F &= 0x3F;
8684
obj->i2c->C1 |= 0x04;
87-
for (i = 0; i < 100; i ++) __NOP();
85+
for (i = 0; i < 100; i ++)
86+
__NOP();
8887
obj->i2c->F |= temp << 6;
8988
} else {
9089
obj->i2c->C1 |= I2C_C1_MST_MASK;
@@ -274,9 +273,8 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
274273
}
275274
}
276275

277-
if (stop) {
276+
if (stop)
278277
i2c_stop(obj);
279-
}
280278

281279
return length;
282280
}
@@ -333,12 +331,15 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
333331
int i2c_slave_receive(i2c_t *obj) {
334332
switch(obj->i2c->S) {
335333
// read addressed
336-
case 0xE6: return 1;
334+
case 0xE6:
335+
return 1;
337336

338337
// write addressed
339-
case 0xE2: return 3;
338+
case 0xE2:
339+
return 3;
340340

341-
default: return 0;
341+
default:
342+
return 0;
342343
}
343344
}
344345

@@ -352,22 +353,19 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
352353

353354
// first dummy read
354355
dummy_read = obj->i2c->D;
355-
if(i2c_wait_end_rx_transfer(obj)) {
356+
if (i2c_wait_end_rx_transfer(obj))
356357
return 0;
357-
}
358358

359359
// read address
360360
dummy_read = obj->i2c->D;
361-
if(i2c_wait_end_rx_transfer(obj)) {
361+
if (i2c_wait_end_rx_transfer(obj))
362362
return 0;
363-
}
364363

365364
// read (length - 1) bytes
366365
for (count = 0; count < (length - 1); count++) {
367366
data[count] = obj->i2c->D;
368-
if (i2c_wait_end_rx_transfer(obj)) {
367+
if (i2c_wait_end_rx_transfer(obj))
369368
return count;
370-
}
371369
}
372370

373371
// read last byte
@@ -384,9 +382,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
384382
obj->i2c->C1 |= I2C_C1_TX_MASK;
385383

386384
for (i = 0; i < length; i++) {
387-
if(i2c_do_write(obj, data[count++]) == 2) {
385+
if (i2c_do_write(obj, data[count++]) == 2)
388386
return i;
389-
}
390387
}
391388

392389
// set rx mode
@@ -395,9 +392,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
395392
// dummy rx transfer needed
396393
// otherwise the master cannot generate a stop bit
397394
obj->i2c->D;
398-
if(i2c_wait_end_rx_transfer(obj) == 2) {
395+
if (i2c_wait_end_rx_transfer(obj) == 2)
399396
return count;
400-
}
401397

402398
return count;
403399
}

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/us_ticker.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,9 @@ static void lptmr_init(void) {
8282
NVIC_EnableIRQ(LPTimer_IRQn);
8383

8484
/* Clock at (1)MHz -> (1)tick/us */
85-
LPTMR0->PSR = LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
85+
OSC0->CR |= OSC_CR_ERCLKEN_MASK;
86+
LPTMR0->PSR = 0;
87+
LPTMR0->PSR |= LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
8688
LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
8789
}
8890

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