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Fix UART write logic issue
1 parent cef6aba commit 79f06c7

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targets/TARGET_RDA/TARGET_UNO_91H/serial_api.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,7 @@ int serial_getc(serial_t *obj)
321321

322322
void serial_putc(serial_t *obj, int c)
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{
324-
while (serial_writable(obj));
324+
while (!serial_writable(obj));
325325
obj->uart->THR = c;
326326
}
327327

@@ -334,12 +334,12 @@ int serial_writable(serial_t *obj)
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{
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int isWritable = 1;
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if (obj->index == 0) {
337-
return (obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control
337+
return !(obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control
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} else {
339339
if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_cts.pin)) //If flow control: writable if CTS low + UART done
340-
isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->FSR & TXFIFO_FULL_MASK);
340+
isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && !(obj->uart->FSR & TXFIFO_FULL_MASK);
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else
342-
isWritable = (obj->uart->FSR & TXFIFO_FULL_MASK);
342+
isWritable = !(obj->uart->FSR & TXFIFO_FULL_MASK);
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return isWritable;
344344
}
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}

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