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STM32Cube_FW_WB_V1.4.0 - STM32WB50xx part
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‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xx/TOOLCHAIN_ARM_STD/startup_stm32wb50xx.S

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;******************************************************************************
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;* File Name : startup_stm32wb50xx_cm4.s
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;* Author : MCD Application Team
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;* Description : STM32WB50xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_PVM_IRQHandler ; PVD and PVM detector
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DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
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DCD FLASH_IRQHandler ; FLASH global Interrupt
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DCD RCC_IRQHandler ; RCC Interrupt
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DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
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DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
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DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
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DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
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DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
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DCD ADC1_IRQHandler ; ADC1 Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
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DCD 0 ; Reserved
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DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
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DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
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DCD TIM2_IRQHandler ; TIM2 Global Interrupt
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DCD PKA_IRQHandler ; PKA Interrupt
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DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
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DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI1_IRQHandler ; SPI1 Interrupt
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DCD 0 ; Reserved
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DCD USART1_IRQHandler ; USART1 Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TSC_IRQHandler ; TSC Interrupt
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DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
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DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
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DCD 0 ; Reserved
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DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
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DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
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DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
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DCD HSEM_IRQHandler ; HSEM0 Interrupt
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DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
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DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD AES2_IRQHandler ; AES2 Interrupt
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DCD RNG_IRQHandler ; RNG1 Interrupt
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DCD FPU_IRQHandler ; FPU Interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_PVM_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_IRQHandler [WEAK]
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EXPORT DMA1_Channel5_IRQHandler [WEAK]
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EXPORT DMA1_Channel6_IRQHandler [WEAK]
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EXPORT DMA1_Channel7_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT PKA_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT TSC_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
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EXPORT IPCC_C1_RX_IRQHandler [WEAK]
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EXPORT IPCC_C1_TX_IRQHandler [WEAK]
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EXPORT HSEM_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT LPTIM2_IRQHandler [WEAK]
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EXPORT AES2_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_PVM_IRQHandler
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TAMP_STAMP_LSECSS_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_IRQHandler
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DMA1_Channel4_IRQHandler
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DMA1_Channel5_IRQHandler
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DMA1_Channel6_IRQHandler
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DMA1_Channel7_IRQHandler
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ADC1_IRQHandler
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C2SEV_PWR_C2H_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_IRQHandler
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TIM1_UP_TIM16_IRQHandler
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TIM1_TRG_COM_TIM17_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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PKA_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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SPI1_IRQHandler
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USART1_IRQHandler
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TSC_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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IPCC_C1_RX_IRQHandler
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IPCC_C1_TX_IRQHandler
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HSEM_IRQHandler
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LPTIM1_IRQHandler
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LPTIM2_IRQHandler
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AES2_IRQHandler
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RNG_IRQHandler
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FPU_IRQHandler
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DMAMUX1_OVR_IRQHandler
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B .
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ENDP
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ALIGN
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;*******************************************************************************
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; User Stack and Heap initialization
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;*******************************************************************************
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xx/TOOLCHAIN_ARM_STD/stm32wb50xx.sct

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#! armcc -E
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; Scatter-Loading Description File
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2016-2020 STMicroelectronics.
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;* All rights reserved.
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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#include "../cmsis_nvic.h"
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#if !defined(MBED_APP_START)
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#define MBED_APP_START MBED_ROM_START
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE MBED_ROM_SIZE
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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/* Round up VECTORS_SIZE to 8 bytes */
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#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE {
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ER_IROM1 MBED_APP_START MBED_APP_SIZE {
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
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}
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ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down
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}
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}

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