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bulislaw0xc0170
bulislaw
authored and
0xc0170
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Modify CMSIS 5 so it is suitable for mbed-os
Make changes to the files taken from RTX5/CMSIS5 so they work with mbed-os and uvisor.
1 parent 7ae2e6e commit 7b022f8

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15 files changed

+115
-27
lines changed

15 files changed

+115
-27
lines changed

‎cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -232,7 +232,7 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
232232
\return Processor Mode
233233
*/
234234
__STATIC_INLINE uint32_t __get_mode(void) {
235-
return (__get_CPSR() & 0x1FU);
235+
return (__get_CPSR() & 0x1FU);
236236
}
237237

238238
/** \brief Set Mode

‎cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,7 @@ __STATIC_INLINE uint32_t __get_CPSR(void)
224224
\return Processor Mode
225225
*/
226226
__STATIC_INLINE uint32_t __get_mode(void) {
227-
return (__get_CPSR() & 0x1FU);
227+
return (__get_CPSR() & 0x1FU);
228228
}
229229

230230
/** \brief Set Mode
@@ -579,24 +579,24 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
579579
*/
580580
__STATIC_INLINE void __FPU_Enable(void) {
581581
__ASM volatile(
582-
//Permit access to VFP/NEON, registers by modifying CPACR
582+
//Permit access to VFP/NEON, registers by modifying CPACR
583583
" MRC p15,0,R1,c1,c0,2 \n"
584584
" ORR R1,R1,#0x00F00000 \n"
585585
" MCR p15,0,R1,c1,c0,2 \n"
586586

587-
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
587+
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
588588
" ISB \n"
589589

590-
//Enable VFP/NEON
590+
//Enable VFP/NEON
591591
" VMRS R1,FPEXC \n"
592592
" ORR R1,R1,#0x40000000 \n"
593593
" VMSR FPEXC,R1 \n"
594594

595-
//Initialise VFP/NEON registers to 0
595+
//Initialise VFP/NEON registers to 0
596596
" MOV R2,#0 \n"
597597
#if 0 // TODO: Initialize FPU registers according to available register count
598598
".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
599-
//Initialise D16 registers to 0
599+
//Initialise D16 registers to 0
600600
" VMOV D0, R2,R2 \n"
601601
" VMOV D1, R2,R2 \n"
602602
" VMOV D2, R2,R2 \n"
@@ -616,7 +616,7 @@ __STATIC_INLINE void __FPU_Enable(void) {
616616
".endif \n"
617617

618618
".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
619-
//Initialise D32 registers to 0
619+
//Initialise D32 registers to 0
620620
" VMOV D16,R2,R2 \n"
621621
" VMOV D17,R2,R2 \n"
622622
" VMOV D18,R2,R2 \n"
@@ -635,7 +635,7 @@ __STATIC_INLINE void __FPU_Enable(void) {
635635
" VMOV D31,R2,R2 \n"
636636
".endif \n"
637637
#endif
638-
//Initialise FPSCR to a known state
638+
//Initialise FPSCR to a known state
639639
" VMRS R2,FPSCR \n"
640640
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
641641
" AND R2,R2,R3 \n"

‎cmsis/TARGET_CORTEX_M/cmsis_compiler.h

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,26 @@
6565

6666
#include <cmsis_iar.h>
6767

68+
/* CMSIS compiler control architecture macros */
69+
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
70+
#ifndef __ARM_ARCH_6M__
71+
#define __ARM_ARCH_6M__ 1
72+
#endif
73+
#elif (__CORE__ == __ARM7M__)
74+
#ifndef __ARM_ARCH_7M__
75+
#define __ARM_ARCH_7M__ 1
76+
#endif
77+
#elif (__CORE__ == __ARM7EM__)
78+
#ifndef __ARM_ARCH_7EM__
79+
#define __ARM_ARCH_7EM__ 1
80+
#endif
81+
#endif
82+
83+
// IAR version 7.8.1 and earlier do not include __ALIGNED
84+
#ifndef __ALIGNED
85+
#define __ALIGNED(x) __attribute__((aligned(x)))
86+
#endif
87+
6888
#ifndef __NO_RETURN
6989
#define __NO_RETURN __noreturn
7090
#endif

‎cmsis/arm_math.h

Lines changed: 34 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -293,14 +293,30 @@
293293
#ifndef _ARM_MATH_H
294294
#define _ARM_MATH_H
295295

296-
/* ignore some GCC warnings */
297-
#if defined ( __GNUC__ )
296+
/* Compiler specific diagnostic adjustment */
297+
#if defined ( __CC_ARM )
298+
299+
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
300+
301+
#elif defined ( __GNUC__ )
298302
#pragma GCC diagnostic push
299303
#pragma GCC diagnostic ignored "-Wsign-conversion"
300304
#pragma GCC diagnostic ignored "-Wconversion"
301305
#pragma GCC diagnostic ignored "-Wunused-parameter"
306+
307+
#elif defined ( __ICCARM__ )
308+
309+
#elif defined ( __TI_ARM__ )
310+
311+
#elif defined ( __CSMC__ )
312+
313+
#elif defined ( __TASKING__ )
314+
315+
#else
316+
#error Unknown compiler
302317
#endif
303318

319+
304320
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
305321

306322
#if defined(ARM_MATH_CM7)
@@ -7213,9 +7229,24 @@ void arm_rfft_fast_f32(
72137229
}
72147230
#endif
72157231

7232+
/* Compiler specific diagnostic adjustment */
7233+
#if defined ( __CC_ARM )
7234+
7235+
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
72167236

7217-
#if defined ( __GNUC__ )
7237+
#elif defined ( __GNUC__ )
72187238
#pragma GCC diagnostic pop
7239+
7240+
#elif defined ( __ICCARM__ )
7241+
7242+
#elif defined ( __TI_ARM__ )
7243+
7244+
#elif defined ( __CSMC__ )
7245+
7246+
#elif defined ( __TASKING__ )
7247+
7248+
#else
7249+
#error Unknown compiler
72197250
#endif
72207251

72217252
#endif /* _ARM_MATH_H */

‎rtos/rtx/cmsis_os.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -433,23 +433,23 @@ uint32_t osKernelSysTick (void);
433433
/// \param instances number of possible thread instances.
434434
/// \param stacksz stack size (in bytes) requirements for the thread function.
435435
#if defined (osObjectsExternal) // object is external
436-
#define osThreadDef(name, priority, instances, stacksz) \
436+
#define osThreadDef(name, priority, stacksz) \
437437
extern const osThreadDef_t os_thread_def_##name
438438
#else // define the object
439439
#if (osCMSIS < 0x20000U)
440-
#define osThreadDef(name, priority, instances, stacksz) \
440+
#define osThreadDef(name, priority, stacksz) \
441441
const osThreadDef_t os_thread_def_##name = \
442-
{ (name), (priority), (instances), (stacksz) }
442+
{ (name), (priority), (1), (stacksz) }
443443
#else
444-
#define osThreadDef(name, priority, instances, stacksz) \
445-
static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
444+
#define osThreadDef(name, priority, stacksz) \
445+
uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
446446
static osRtxThread_t os_thread_cb_##name __attribute__((section(".bss.os.thread.cb"))); \
447447
const osThreadDef_t os_thread_def_##name = \
448448
{ (name), \
449449
{ NULL, osThreadDetached, \
450-
(instances == 1) ? (&os_thread_cb_##name) : NULL,\
451-
(instances == 1) ? osRtxThreadCbSize : 0U, \
452-
((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
450+
(&os_thread_cb_##name),\
451+
osRtxThreadCbSize, \
452+
(stacksz) ? (&os_thread_stack##name) : NULL, \
453453
8*((stacksz+7)/8), \
454454
(priority), 0U, 0U } }
455455
#endif

‎rtos/rtx2/TARGET_CORTEX_M/RTX_Config.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
*
2525
* -----------------------------------------------------------------------------
2626
*/
27-
27+
2828
#include "cmsis_compiler.h"
2929
#include "rtx_os.h"
3030

‎rtos/rtx2/TARGET_CORTEX_M/RTX_Config.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
/** \addtogroup rtos */
2+
/** @{*/
13
/*
24
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
35
*
@@ -27,7 +29,9 @@
2729

2830
#ifndef RTX_CONFIG_H_
2931
#define RTX_CONFIG_H_
30-
32+
33+
#include "rtx2/mbed_rtx_conf.h"
34+
3135
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
3236

3337
// <h>System Configuration
@@ -377,3 +381,4 @@
377381
//------------- <<< end of configuration section >>> ---------------------------
378382

379383
#endif // RTX_CONFIG_H_
384+
/** @}*/

‎rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,16 +66,20 @@ SVC_Context
6666
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
6767
TST LR,#0x10 ; Check if extended stack frame
6868
BNE SVC_ContextSwitch
69+
#ifdef __FPU_PRESENT
6970
LDR R1,=0xE000EF34 ; FPCCR Address
7071
LDR R0,[R1] ; Load FPCCR
7172
BIC R0,#1 ; Clear LSPACT (Lazy state)
7273
STR R0,[R1] ; Store FPCCR
7374
B SVC_ContextSwitch
75+
#endif
7476

7577
SVC_ContextSave
7678
STMDB R12!,{R4-R11} ; Save R4..R11
79+
#ifdef __FPU_PRESENT
7780
TST LR,#0x10 ; Check if extended stack frame
7881
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
82+
#endif
7983

8084
STR R12,[R1,#TCB_SP_OFS] ; Store SP
8185
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@@ -88,8 +92,10 @@ SVC_ContextRestore
8892
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
8993
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
9094

95+
#ifdef __FPU_PRESENT
9196
TST LR,#0x10 ; Check if extended stack frame
9297
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
98+
#endif
9399
LDMIA R0!,{R4-R11} ; Restore R4..R11
94100
MSR PSP,R0 ; Set PSP
95101

‎rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,17 +70,22 @@ SVC_Context:
7070
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
7171
TST LR,#0x10 // Check if extended stack frame
7272
BNE SVC_ContextSwitch
73+
#ifdef __FPU_PRESENT
7374
LDR R1,=0xE000EF34 // FPCCR Address
7475
LDR R0,[R1] // Load FPCCR
7576
BIC R0,#1 // Clear LSPACT (Lazy state)
7677
STR R0,[R1] // Store FPCCR
7778
B SVC_ContextSwitch
79+
#endif
7880

7981
SVC_ContextSave:
8082
STMDB R12!,{R4-R11} // Save R4..R11
83+
84+
#ifdef __FPU_PRESENT
8185
TST LR,#0x10 // Check if extended stack frame
8286
IT EQ
8387
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
88+
#endif
8489

8590
STR R12,[R1,#TCB_SP_OFS] // Store SP
8691
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
@@ -93,9 +98,11 @@ SVC_ContextRestore:
9398
LDR R0,[R2,#TCB_SP_OFS] // Load SP
9499
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
95100

101+
#ifdef __FPU_PRESENT
96102
TST LR,#0x10 // Check if extended stack frame
97103
IT EQ
98104
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
105+
#endif
99106
LDMIA R0!,{R4-R11} // Restore R4..R11
100107
MSR PSP,R0 // Set PSP
101108

‎rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,17 +69,21 @@ SVC_Context
6969
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
7070
TST LR,#0x10 ; Check if extended stack frame
7171
BNE SVC_ContextSwitch
72+
#ifdef __FPU_PRESENT
7273
LDR R1,=0xE000EF34 ; FPCCR Address
7374
LDR R0,[R1] ; Load FPCCR
7475
BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
7576
STR R0,[R1] ; Store FPCCR
7677
B SVC_ContextSwitch
78+
#endif
7779

7880
SVC_ContextSave
7981
STMDB R12!,{R4-R11} ; Save R4..R11
82+
#ifdef __FPU_PRESENT
8083
TST LR,#0x10 ; Check if extended stack frame
8184
IT EQ
8285
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
86+
#endif
8387

8488
STR R12,[R1,#TCB_SP_OFS] ; Store SP
8589
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@@ -92,9 +96,11 @@ SVC_ContextRestore
9296
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
9397
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
9498

99+
#ifdef __FPU_PRESENT
95100
TST LR,#0x10 ; Check if extended stack frame
96101
IT EQ
97102
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
103+
#endif
98104
LDMIA R0!,{R4-R11} ; Restore R4..R11
99105
MSR PSP,R0 ; Set PSP
100106

‎rtos/rtx2/TARGET_CORTEX_M/cmsis_os2.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
/** \addtogroup rtos */
2+
/** @{*/
13
/*
24
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
35
*
@@ -744,3 +746,5 @@ osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
744746
#endif
745747

746748
#endif // CMSIS_OS2_H_
749+
750+
/** @}*/

‎rtos/rtx2/TARGET_CORTEX_M/core_cm.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
/** \addtogroup rtos */
2+
/** @{*/
13
/*
24
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
35
*
@@ -26,8 +28,10 @@
2628
#ifndef CORE_CM_H_
2729
#define CORE_CM_H_
2830

29-
#include "RTE_Components.h"
30-
#include CMSIS_device_header
31+
#include <stdint.h>
32+
#include "cmsis.h"
33+
#include "cmsis_compiler.h"
34+
#include "arm_math.h"
3135

3236
#ifndef __ARM_ARCH_6M__
3337
#define __ARM_ARCH_6M__ 0U
@@ -1526,3 +1530,5 @@ __STATIC_INLINE void atomic_link_put (void **root, void *link) {
15261530

15271531

15281532
#endif // CORE_CM_H_
1533+
1534+
/** @}*/

‎rtos/rtx2/TARGET_CORTEX_M/rtx_evr.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,6 @@
2727
#include "cmsis_compiler.h"
2828
#include "rtx_evr.h" // RTX Event Recorder definitions
2929

30-
#include "RTE_Components.h"
31-
3230
#ifdef RTE_Compiler_EventRecorder
3331

3432
#include "EventRecorder.h" // Keil::Compiler:Event Recorder

‎rtos/rtx2/TARGET_CORTEX_M/rtx_evr.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
/** \addtogroup rtos */
2+
/** @{*/
13
/*
24
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
35
*
@@ -1842,3 +1844,4 @@ extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id);
18421844

18431845

18441846
#endif // RTX_EVR_H_
1847+
/** @}*/

‎rtos/rtx2/TARGET_CORTEX_M/rtx_lib.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
/** \addtogroup rtos */
2+
/** @{*/
13
/*
24
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
35
*
@@ -210,5 +212,5 @@ extern uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_i
210212
extern osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id);
211213
extern osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id);
212214

213-
214215
#endif // RTX_LIB_H_
216+
/** @}*/

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