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Commit 7b334b2

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Matthew Macovsky
committed
Allow for arbitrary QSPI alt sizes (WIP)
This is an early proof of concept. In particular, the Silicon Labs driver has not been updated yet to support the new scheme.
1 parent 671c2fb commit 7b334b2

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10 files changed

+291
-142
lines changed

10 files changed

+291
-142
lines changed

‎components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp

Lines changed: 34 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -169,8 +169,7 @@ int QSPIFBlockDevice::init()
169169
_inst_width = QSPI_CFG_BUS_SINGLE;
170170
_address_width = QSPI_CFG_BUS_SINGLE;
171171
_address_size = QSPI_CFG_ADDR_SIZE_24;
172-
_alt_size = QSPI_CFG_ALT_SIZE_8;
173-
_alt_enabled = false;
172+
_alt_size = 0;
174173
_dummy_cycles = 0;
175174
_data_width = QSPI_CFG_BUS_SINGLE;
176175
_write_register_inst = QSPIF_WRSR;
@@ -248,8 +247,11 @@ int QSPIFBlockDevice::init()
248247
}
249248

250249
// Configure BUS Mode to 1_1_1 for all commands other than Read
251-
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
252-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
250+
if (QSPI_STATUS_OK != _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
251+
0, QSPI_CFG_BUS_SINGLE, 0)) {
252+
status = QSPIF_BD_ERROR_CONF_FORMAT_FAILED;
253+
goto exit_point;
254+
}
253255

254256
_is_initialized = true;
255257

@@ -304,17 +306,21 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
304306
_mutex.lock();
305307

306308
// Configure Bus for Reading
307-
_qspi_configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width == address width
308-
_alt_size, _data_width, _dummy_cycles);
309+
if (QSPI_STATUS_OK != _qspi_configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width == address width
310+
_alt_size, _data_width, _dummy_cycles)) {
311+
return QSPIF_BD_ERROR_CONF_FORMAT_FAILED;
312+
}
309313

310314
if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) {
311-
status = QSPIF_BD_ERROR_DEVICE_ERROR;
312315
tr_error("Read Command failed");
316+
return QSPIF_BD_ERROR_DEVICE_ERROR;
313317
}
314318

315319
// All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
316-
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
317-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
320+
if (QSPI_STATUS_OK != _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
321+
0, QSPI_CFG_BUS_SINGLE, 0)) {
322+
return QSPIF_BD_ERROR_CONF_FORMAT_FAILED;
323+
}
318324

319325
_mutex.unlock();
320326
return status;
@@ -719,8 +725,10 @@ int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_
719725
bd_addr_t addr = 0x0;
720726

721727
// Set 1-1-1 bus mode for SFDP header parsing
722-
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
723-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 8);
728+
if (QSPI_STATUS_OK != _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
729+
0, QSPI_CFG_BUS_SINGLE, 8)) {
730+
return -1;
731+
}
724732

725733
qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sfdp_header, addr /*address*/, data_length);
726734
if (status != QSPI_STATUS_OK) {
@@ -886,8 +894,10 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr)
886894
}
887895

888896
// Configure BUS Mode to 1_1_1 for all commands other than Read
889-
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
890-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
897+
if (QSPI_STATUS_OK != _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
898+
0, QSPI_CFG_BUS_SINGLE, 0)) {
899+
return -1;
900+
}
891901

892902
// Read Status Register
893903
if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1028,7 +1038,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10281038
is_qpi_mode = true;
10291039
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F;
10301040
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5;
1031-
_utils_determine_alt_size(mode_cycles * 4);
1041+
_alt_size = mode_cycles * 4;
10321042
tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction);
10331043
//_inst_width = QSPI_CFG_BUS_QUAD;
10341044
_address_width = QSPI_CFG_BUS_QUAD;
@@ -1043,7 +1053,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10431053
set_quad_enable = true;
10441054
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F;
10451055
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5;
1046-
_utils_determine_alt_size(mode_cycles * 4);
1056+
_alt_size = mode_cycles * 4;
10471057
_address_width = QSPI_CFG_BUS_QUAD;
10481058
_data_width = QSPI_CFG_BUS_QUAD;
10491059
tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction);
@@ -1056,7 +1066,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10561066
set_quad_enable = true;
10571067
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F;
10581068
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5;
1059-
_utils_determine_alt_size(mode_cycles);
1069+
_alt_size = mode_cycles;
10601070
_data_width = QSPI_CFG_BUS_QUAD;
10611071
tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction);
10621072
break;
@@ -1067,7 +1077,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10671077
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE];
10681078
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F;
10691079
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5;
1070-
_utils_determine_alt_size(mode_cycles * 2);
1080+
_alt_size = mode_cycles * 2;
10711081
_address_width = QSPI_CFG_BUS_DUAL;
10721082
_data_width = QSPI_CFG_BUS_DUAL;
10731083
tr_debug("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1080,7 +1090,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10801090
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE];
10811091
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F;
10821092
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5;
1083-
_utils_determine_alt_size(mode_cycles * 2);
1093+
_alt_size = mode_cycles * 2;
10841094
_address_width = QSPI_CFG_BUS_DUAL;
10851095
_data_width = QSPI_CFG_BUS_DUAL;
10861096
tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1091,7 +1101,7 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10911101
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE];
10921102
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F;
10931103
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5;
1094-
_utils_determine_alt_size(mode_cycles);
1104+
_alt_size = mode_cycles;
10951105
_data_width = QSPI_CFG_BUS_DUAL;
10961106
tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction);
10971107
break;
@@ -1212,8 +1222,10 @@ int QSPIFBlockDevice::_enable_fast_mdoe()
12121222
status_reg_qer_setup[2] = 0x2; // Bit 1 of config Reg 2
12131223

12141224
// Configure BUS Mode to 1_1_1 for all commands other than Read
1215-
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
1216-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
1225+
if (QSPI_STATUS_OK != _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
1226+
0, QSPI_CFG_BUS_SINGLE, 0)) {
1227+
return -1;
1228+
}
12171229

12181230
// Read Status Register
12191231
if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1315,28 +1327,6 @@ int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield,
13151327
return largest_erase_type;
13161328
}
13171329

1318-
void QSPIFBlockDevice::_utils_determine_alt_size(uint8_t mode_bits)
1319-
{
1320-
_alt_enabled = true;
1321-
switch (mode_bits) {
1322-
case 8:
1323-
_alt_size = QSPI_CFG_ALT_SIZE_8;
1324-
break;
1325-
case 16:
1326-
_alt_size = QSPI_CFG_ALT_SIZE_16;
1327-
break;
1328-
case 24:
1329-
_alt_size = QSPI_CFG_ALT_SIZE_24;
1330-
break;
1331-
case 32:
1332-
_alt_size = QSPI_CFG_ALT_SIZE_32;
1333-
break;
1334-
default:
1335-
_alt_enabled = false;
1336-
break;
1337-
}
1338-
}
1339-
13401330
/***************************************************/
13411331
/*********** QSPI Driver API Functions *************/
13421332
/***************************************************/
@@ -1351,7 +1341,7 @@ qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(unsigned int read_inst,
13511341
// Send Read command to device driver
13521342
size_t buf_len = size;
13531343

1354-
if (_qspi.read(read_inst, _alt_enabled ? QSPI_ALT_DEFAULT_VALUE : -1, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
1344+
if (_qspi.read(read_inst, (_alt_size == 0) ? -1 : QSPI_ALT_DEFAULT_VALUE, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
13551345
tr_error("Read failed");
13561346
return QSPI_STATUS_ERROR;
13571347
}

‎components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,10 @@ enum qspif_bd_error {
2929
QSPIF_BD_ERROR_PARSING_FAILED = -4002, /* SFDP Parsing failed */
3030
QSPIF_BD_ERROR_READY_FAILED = -4003, /* Wait for Mem Ready failed */
3131
QSPIF_BD_ERROR_WREN_FAILED = -4004, /* Write Enable Failed */
32-
QSPIF_BD_ERROR_INVALID_ERASE_PARAMS = -4005, /* Erase command not on sector aligned addresses or exceeds device size */
33-
QSPIF_BD_ERROR_DEVICE_NOT_UNIQE = -4006, /* Only one instance per csel is allowed */
34-
QSPIF_BD_ERROR_DEVICE_MAX_EXCEED = -4007 /* Max active QSPIF devices exceeded */
32+
QSPIF_BD_ERROR_CONF_FORMAT_FAILED = -4005, /* Configure format failed */
33+
QSPIF_BD_ERROR_INVALID_ERASE_PARAMS = -4006, /* Erase command not on sector aligned addresses or exceeds device size */
34+
QSPIF_BD_ERROR_DEVICE_NOT_UNIQE = -4007, /* Only one instance per csel is allowed */
35+
QSPIF_BD_ERROR_DEVICE_MAX_EXCEED = -4008 /* Max active QSPIF devices exceeded */
3536
};
3637

3738
/** Enum qspif polarity mode
@@ -312,9 +313,6 @@ class QSPIFBlockDevice : public mbed::BlockDevice {
312313
// Iterates from highest type to lowest
313314
int _utils_iterate_next_largest_erase_type(uint8_t &bitfield, int size, int offset, int boundry);
314315

315-
// Determine alt size from mode bits
316-
void _utils_determine_alt_size(uint8_t mode_bits);
317-
318316
private:
319317
// QSPI Driver Object
320318
mbed::QSPI _qspi;

‎drivers/QSPI.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ class QSPI : private NonCopyable<QSPI> {
106106
* @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
107107
* @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
108108
* @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
109-
* @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
109+
* @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width)
110110
* @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
111111
* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
112112
*

‎drivers/source/QSPI.cpp

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,21 @@ namespace mbed {
2626
QSPI *QSPI::_owner = NULL;
2727
SingletonPtr<PlatformMutex> QSPI::_mutex;
2828

29+
uint8_t convert_bus_width_to_line_count(qspi_bus_width_t width)
30+
{
31+
switch (width) {
32+
case QSPI_CFG_BUS_SINGLE:
33+
return 1;
34+
case QSPI_CFG_BUS_DUAL:
35+
return 2;
36+
case QSPI_CFG_BUS_QUAD:
37+
return 4;
38+
default:
39+
// Unrecognized bus width
40+
return 0;
41+
}
42+
}
43+
2944
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
3045
{
3146
_qspi_io0 = io0;
@@ -38,7 +53,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
3853
_address_width = QSPI_CFG_BUS_SINGLE;
3954
_address_size = QSPI_CFG_ADDR_SIZE_24;
4055
_alt_width = QSPI_CFG_BUS_SINGLE;
41-
_alt_size = QSPI_CFG_ALT_SIZE_8;
56+
_alt_size = 0;
4257
_data_width = QSPI_CFG_BUS_SINGLE;
4358
_num_dummy_cycles = 0;
4459
_mode = mode;
@@ -52,7 +67,14 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
5267

5368
qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
5469
{
55-
qspi_status_t ret_status = QSPI_STATUS_OK;
70+
// Check that alt_size/alt_width are a valid combination
71+
uint8_t alt_lines = convert_bus_width_to_line_count(alt_width);
72+
if (alt_lines == 0) {
73+
return QSPI_STATUS_ERROR;
74+
} else if (alt_size % alt_lines != 0) {
75+
// Invalid alt size/width combination (alt size is not a multiple of the number of bus lines used to transmit it)
76+
return QSPI_STATUS_ERROR;
77+
}
5678

5779
lock();
5880
_inst_width = inst_width;
@@ -62,10 +84,9 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width
6284
_alt_size = alt_size;
6385
_data_width = data_width;
6486
_num_dummy_cycles = dummy_cycles;
65-
6687
unlock();
6788

68-
return ret_status;
89+
return QSPI_STATUS_OK;
6990
}
7091

7192
qspi_status_t QSPI::set_frequency(int hz)

‎features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,7 @@ void test_direct_access_to_device_inject_root()
255255
ret = devkey.device_inject_root_of_trust(key, DEVICE_KEY_16BYTE);
256256
TEST_ASSERT_EQUAL_INT(DEVICEKEY_SUCCESS, ret);
257257

258-
// Now use Direct Access To DeviceKey to retrieve it */
258+
// Now use Direct Access To DeviceKey to retrieve it
259259
uint32_t internal_start_address;
260260
uint32_t internal_rbp_size;
261261
bool is_conf_tdb_internal = false;

‎hal/qspi_api.h

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -60,12 +60,7 @@ typedef enum qspi_address_size {
6060

6161
/** Alternative size in bits
6262
*/
63-
typedef enum qspi_alt_size {
64-
QSPI_CFG_ALT_SIZE_8,
65-
QSPI_CFG_ALT_SIZE_16,
66-
QSPI_CFG_ALT_SIZE_24,
67-
QSPI_CFG_ALT_SIZE_32,
68-
} qspi_alt_size_t;
63+
typedef uint8_t qspi_alt_size_t;
6964

7065
/** QSPI command
7166
*

‎targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -69,21 +69,6 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_addr_size(qspi_address_size_t
6969
}
7070
}
7171

72-
static inline cyhal_qspi_size_t cyhal_qspi_convert_alt_size(qspi_alt_size_t size)
73-
{
74-
switch (size) {
75-
case QSPI_CFG_ALT_SIZE_8:
76-
return CYHAL_QSPI_CFG_SIZE_8;
77-
case QSPI_CFG_ALT_SIZE_16:
78-
return CYHAL_QSPI_CFG_SIZE_16;
79-
case QSPI_CFG_ALT_SIZE_24:
80-
return CYHAL_QSPI_CFG_SIZE_24;
81-
default: // fallthrough
82-
case QSPI_CFG_ALT_SIZE_32:
83-
return CYHAL_QSPI_CFG_SIZE_32;
84-
}
85-
}
86-
8772
static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_command_t *to)
8873
{
8974
to->instruction.bus_width = cyhal_qspi_convert_width(from->instruction.bus_width);
@@ -94,7 +79,7 @@ static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_co
9479
to->address.value = from->address.value;
9580
to->address.disabled = from->address.disabled;
9681
to->mode_bits.bus_width = cyhal_qspi_convert_width(from->alt.bus_width);
97-
to->mode_bits.size = cyhal_qspi_convert_alt_size(from->alt.size);
82+
to->mode_bits.size = from->alt.size;
9883
to->mode_bits.value = from->alt.value;
9984
to->mode_bits.disabled = from->alt.disabled;
10085
to->dummy_count = from->dummy_count;

‎targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,12 @@ typedef enum {
8888
*/
8989

9090
#define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/
91-
#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/
92-
#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/
93-
#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/
91+
#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/
92+
#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/
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#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/
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#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/
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#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/
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#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/
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/** \} group_hal_qspi_macros */
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@@ -115,7 +118,7 @@ typedef struct cyhal_qspi_command {
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} address;
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struct {
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cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/
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cyhal_qspi_size_t size; /**< Mode bits size >*/
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uint8_t size; /**< Mode bits size >*/
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uint32_t value; /**< Mode bits value >*/
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bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/
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} mode_bits;

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