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c1728p90xc0170
c1728p9
authored and
0xc0170
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Fix asyle problems
Run astyle to fix CI failures.
1 parent 02b50b4 commit 7cdfbee

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3 files changed

+26
-26
lines changed

3 files changed

+26
-26
lines changed

‎TESTS/mbed_hal/mpu/main.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -46,11 +46,11 @@ static volatile uint16_t bss_function;
4646
static void clear_caches()
4747
{
4848
#if defined(__CORTEX_M7)
49-
/* Data cache clean and invalid */
50-
SCB_CleanInvalidateDCache();
49+
/* Data cache clean and invalid */
50+
SCB_CleanInvalidateDCache();
5151

52-
/* Instruction cache invalid */
53-
SCB_InvalidateICache();
52+
/* Instruction cache invalid */
53+
SCB_InvalidateICache();
5454
#endif
5555

5656
__ISB();
@@ -61,7 +61,7 @@ static void clear_caches()
6161
static void call_mem(const volatile uint16_t *mem_function)
6262
{
6363
// or the address with 1 to ensure the thumb bit is set
64-
((void (*)()) ((uint32_t)mem_function | 1))();
64+
((void (*)())((uint32_t)mem_function | 1))();
6565
}
6666

6767
static void hard_fault_handler_test()
@@ -144,7 +144,7 @@ void mpu_fault_test_stack()
144144

145145
void mpu_fault_test_heap()
146146
{
147-
uint16_t *heap_function = (uint16_t*)malloc(2);
147+
uint16_t *heap_function = (uint16_t *)malloc(2);
148148

149149
TEST_ASSERT_NOT_EQUAL(NULL, heap_function);
150150
*heap_function = ASM_BX_LR;
@@ -166,7 +166,7 @@ utest::v1::status_t fault_override_setup(const Case *const source, const size_t
166166
}
167167

168168
utest::v1::status_t fault_override_teardown(const Case *const source, const size_t passed, const size_t failed,
169-
const failure_t reason)
169+
const failure_t reason)
170170
{
171171
// Restore real fault handlers
172172
NVIC_SetVector(HARDFAULT_IRQn, real_hard_fault_handler);

‎hal/mpu/mbed_mpu_v7m.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ void mbed_mpu_init()
8888
0, // IsShareable
8989
1, // IsCacheable
9090
0, // IsBufferable
91-
// SubRegionDisable - based on where ROM ends
91+
// SubRegionDisable - based on where ROM ends
9292
((MBED_MPU_ROM_END >= 0x00000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
9393
((MBED_MPU_ROM_END >= 0x04000000) ? 0 : (1 << 1)) |
9494
((MBED_MPU_ROM_END >= 0x08000000) ? 0 : (1 << 2)) |
@@ -114,7 +114,7 @@ void mbed_mpu_init()
114114
0, // IsShareable
115115
1, // IsCacheable
116116
0, // IsBufferable
117-
// SubRegionDisable - based on where RAM starts
117+
// SubRegionDisable - based on where RAM starts
118118
((MBED_MPU_RAM_START <= 0x04000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
119119
((MBED_MPU_RAM_START <= 0x08000000) ? 0 : (1 << 1)) |
120120
((MBED_MPU_RAM_START <= 0x0C000000) ? 0 : (1 << 2)) |
@@ -141,7 +141,7 @@ void mbed_mpu_init()
141141
0, // IsShareable
142142
1, // IsCacheable
143143
1, // IsBufferable
144-
// SubRegionDisable
144+
// SubRegionDisable
145145
(1 << 0) | // Disable Sub-region
146146
(0 << 1) | // Enable Sub-region SRAM 0x20000000 - 0x3FFFFFFF
147147
(1 << 2) | // Disable Sub-region

‎hal/mpu/mbed_mpu_v8m.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -74,47 +74,47 @@ void mbed_mpu_init()
7474
inner = 0xA; // Write-Through, Non-transient, Read-allocate
7575
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
7676
MPU->RBAR = (0x00000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x00000000
77-
(0 << MPU_RBAR_SH_Pos) | // Not shareable
78-
(3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels
79-
(0 << MPU_RBAR_XN_Pos); // Execute Never disabled
77+
(0 << MPU_RBAR_SH_Pos) | // Not shareable
78+
(3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels
79+
(0 << MPU_RBAR_XN_Pos); // Execute Never disabled
8080
MPU->RLAR = (0x1FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x1FFFFFFF
81-
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
81+
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
8282

8383
region = 1;
8484
MPU->RNR = region;
8585
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
8686
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
8787
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
8888
MPU->RBAR = (0x20000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x20000000
89-
(0 << MPU_RBAR_SH_Pos) | // Not shareable
90-
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
91-
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
89+
(0 << MPU_RBAR_SH_Pos) | // Not shareable
90+
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
91+
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
9292
MPU->RLAR = (0x3FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x3FFFFFFF
93-
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
93+
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
9494

9595
region = 2;
9696
MPU->RNR = region;
9797
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
9898
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
9999
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
100100
MPU->RBAR = (0x60000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x60000000
101-
(0 << MPU_RBAR_SH_Pos) | // Not shareable
102-
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
103-
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
101+
(0 << MPU_RBAR_SH_Pos) | // Not shareable
102+
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
103+
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
104104
MPU->RLAR = (0x7FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x7FFFFFFF
105-
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
105+
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
106106

107107
region = 3;
108108
MPU->RNR = region;
109109
outer = 0xA; // Write-Through, Non-transient, Read-allocate
110110
inner = 0xA; // Write-Through, Non-transient, Read-allocate
111111
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
112112
MPU->RBAR = (0x80000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x80000000
113-
(0 << MPU_RBAR_SH_Pos) | // Not shareable
114-
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
115-
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
113+
(0 << MPU_RBAR_SH_Pos) | // Not shareable
114+
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
115+
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
116116
MPU->RLAR = (0x9FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x9FFFFFFF
117-
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
117+
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
118118

119119
// Enable the MPU
120120
MPU->CTRL =

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