MCUXpresso: Update Kinetis SPI SDK drivers

Added dummy data setup API to allow users to configure
the dummy data to be transferred.

Signed-off-by: Mahesh Mahadevan <[email protected]>

Author: mmahadevan108

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_spi.c

@@ -1,31 +1,9 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used tom  endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_SPI_H_
 #define _FSL_SPI_H_
@@ -37,28 +15,30 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SPI driver version 2.0.1. */
-#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief SPI driver version 2.0.4. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
 /*@}*/
 
 #ifndef SPI_DUMMYDATA
 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
 #define SPI_DUMMYDATA (0xFFU)
 #endif
 
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t g_spiDummyData[];
+
 /*! @brief Return status for the SPI driver.*/
 enum _spi_status
 {
-    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
-    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
-    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) /*!< SPI  error */
+    kStatus_SPI_Busy  = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
+    kStatus_SPI_Idle  = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
+    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2)  /*!< SPI  error */
 };
 
 /*! @brief SPI clock polarity configuration.*/
@@ -87,16 +67,16 @@ typedef enum _spi_shift_direction
 /*! @brief SPI slave select output mode options.*/
 typedef enum _spi_ss_output_mode
 {
-    kSPI_SlaveSelectAsGpio = 0x0U,         /*!< Slave select pin configured as GPIO. */
-    kSPI_SlaveSelectFaultInput = 0x2U,     /*!< Slave select pin configured for fault detection. */
-    kSPI_SlaveSelectAutomaticOutput = 0x3U /*!< Slave select pin configured for automatic SPI output. */
+    kSPI_SlaveSelectAsGpio          = 0x0U, /*!< Slave select pin configured as GPIO. */
+    kSPI_SlaveSelectFaultInput      = 0x2U, /*!< Slave select pin configured for fault detection. */
+    kSPI_SlaveSelectAutomaticOutput = 0x3U  /*!< Slave select pin configured for automatic SPI output. */
 } spi_ss_output_mode_t;
 
 /*! @brief SPI pin mode options.*/
 typedef enum _spi_pin_mode
 {
     kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/
-    kSPI_PinModeInput = 0x1U,  /*!< Bidirectional mode. Master: MOSI pin is input;
+    kSPI_PinModeInput  = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input;
                                 *   Slave: MISO pin is input. */
     kSPI_PinModeOutput = 0x3U  /*!< Bidirectional mode. Master: MOSI pin is output;
                                 *   Slave: MISO pin is output. */
@@ -113,64 +93,64 @@ typedef enum _spi_data_bitcount_mode
 enum _spi_interrupt_enable
 {
     kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
-    kSPI_TxEmptyInterruptEnable = 0x2U,       /*!< Transmit buffer empty interrupt */
-    kSPI_MatchInterruptEnable = 0x4U,         /*!< Match interrupt */
+    kSPI_TxEmptyInterruptEnable       = 0x2U, /*!< Transmit buffer empty interrupt */
+    kSPI_MatchInterruptEnable         = 0x4U, /*!< Match interrupt */
 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
-    kSPI_RxFifoNearFullInterruptEnable = 0x8U,   /*!< Receive FIFO nearly full interrupt */
+    kSPI_RxFifoNearFullInterruptEnable  = 0x8U,  /*!< Receive FIFO nearly full interrupt */
     kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */
 #endif                                           /* FSL_FEATURE_SPI_HAS_FIFO */
 };
 
 /*! @brief SPI status flags.*/
 enum _spi_flags
 {
-    kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK,   /*!< Read buffer full flag */
-    kSPI_MatchFlag = SPI_S_SPMF_MASK,          /*!< Match flag */
+    kSPI_RxBufferFullFlag  = SPI_S_SPRF_MASK,  /*!< Read buffer full flag */
+    kSPI_MatchFlag         = SPI_S_SPMF_MASK,  /*!< Match flag */
     kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */
-    kSPI_ModeFaultFlag = SPI_S_MODF_MASK,      /*!< Mode fault flag */
+    kSPI_ModeFaultFlag     = SPI_S_MODF_MASK,  /*!< Mode fault flag */
 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
-    kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK,  /*!< Rx FIFO near full */
-    kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, /*!< Tx FIFO near empty */
-    kSPI_TxFifoFullFlag = SPI_S_TXFULLF_MASK,      /*!< Tx FIFO full */
-    kSPI_RxFifoEmptyFlag = SPI_S_RFIFOEF_MASK,     /*!< Rx FIFO empty */
-    kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U,   /*!< Tx FIFO error */
-    kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U,   /*!< Rx FIFO error */
-    kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U,     /*!< Tx FIFO Overflow */
-    kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U      /*!< Rx FIFO Overflow */
-#endif                                             /* FSL_FEATURE_SPI_HAS_FIFO */
+    kSPI_RxFifoNearFullFlag  = SPI_S_RNFULLF_MASK,       /*!< Rx FIFO near full */
+    kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK,       /*!< Tx FIFO near empty */
+    kSPI_TxFifoFullFlag      = SPI_S_TXFULLF_MASK,       /*!< Tx FIFO full */
+    kSPI_RxFifoEmptyFlag     = SPI_S_RFIFOEF_MASK,       /*!< Rx FIFO empty */
+    kSPI_TxFifoError         = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */
+    kSPI_RxFifoError         = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO error */
+    kSPI_TxOverflow          = SPI_CI_TXFOF_MASK << 8U,  /*!< Tx FIFO Overflow */
+    kSPI_RxOverflow          = SPI_CI_RXFOF_MASK << 8U   /*!< Rx FIFO Overflow */
+#endif                                                   /* FSL_FEATURE_SPI_HAS_FIFO */
 };
 
 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
 /*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
 typedef enum _spi_w1c_interrupt
 {
-    kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK,    /*!< Receive FIFO full interrupt */
-    kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK,  /*!< Transmit FIFO empty interrupt */
-    kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
-    kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK /*!< Transmit FIFO nearly empty interrupt */
+    kSPI_RxFifoFullClearInterrupt  = SPI_CI_SPRFCI_MASK,    /*!< Receive FIFO full interrupt */
+    kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK,   /*!< Transmit FIFO empty interrupt */
+    kSPI_RxNearFullClearInterrupt  = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
+    kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK  /*!< Transmit FIFO nearly empty interrupt */
 } spi_w1c_interrupt_t;
 
 /*! @brief SPI TX FIFO watermark settings.*/
 typedef enum _spi_txfifo_watermark
 {
     kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */
-    kSPI_TxFifoOneHalfEmpty = 1    /*!< SPI tx watermark at 1/2 FIFO size */
+    kSPI_TxFifoOneHalfEmpty   = 1  /*!< SPI tx watermark at 1/2 FIFO size */
 } spi_txfifo_watermark_t;
 
 /*! @brief SPI RX FIFO watermark settings.*/
 typedef enum _spi_rxfifo_watermark
 {
     kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */
-    kSPI_RxFifoOneHalfFull = 1       /*!< SPI rx watermark at 1/2 FIFO size */
+    kSPI_RxFifoOneHalfFull      = 1  /*!< SPI rx watermark at 1/2 FIFO size */
 } spi_rxfifo_watermark_t;
 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
 
 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
 /*! @brief SPI DMA source*/
 enum _spi_dma_enable_t
 {
-    kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK,                        /*!< Tx DMA request source */
-    kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK,                        /*!< Rx DMA request source */
+    kSPI_TxDmaEnable  = SPI_C2_TXDMAE_MASK,                       /*!< Tx DMA request source */
+    kSPI_RxDmaEnable  = SPI_C2_RXDMAE_MASK,                       /*!< Rx DMA request source */
     kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/
 };
 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
@@ -210,6 +190,7 @@ typedef struct _spi_slave_config
     spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
     spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
 #endif                                  /* FSL_FEATURE_SPI_HAS_FIFO */
+    spi_pin_mode_t pinMode;             /*!< SPI pin mode select */
 } spi_slave_config_t;
 
 /*! @brief SPI transfer structure */
@@ -478,6 +459,27 @@ static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
  * @{
  */
 
+/*!
+ * @brief Get the instance for SPI module.
+ *
+ * @param base SPI base address
+ */
+uint32_t SPI_GetInstance(SPI_Type *base);
+
+/*!
+ * @brief Sets the pin mode for transfer.
+ *
+ * @param base SPI base pointer
+ * @param pinMode pin mode for transfer AND #_spi_pin_mode could get the related configuration.
+ */
+static inline void SPI_SetPinMode(SPI_Type *base, spi_pin_mode_t pinMode)
+{
+    /* Clear SPC0 and BIDIROE bit. */
+    base->C2 &= ~(SPI_C2_BIDIROE_MASK | SPI_C2_SPC0_MASK);
+    /* Set pin mode for transfer. */
+    base->C2 |= SPI_C2_BIDIROE(pinMode >> 1U) | SPI_C2_SPC0(pinMode & 1U);
+}
+
 /*!
  * @brief Sets the baud rate for SPI transfer. This is only used in master.
  *
@@ -544,6 +546,13 @@ void SPI_WriteData(SPI_Type *base, uint16_t data);
  */
 uint16_t SPI_ReadData(SPI_Type *base);
 
+/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base SPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
 /*! @} */
 
 /*!
@@ -582,11 +591,7 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
  *
  * @note The API immediately returns after transfer initialization is finished.
  * Call SPI_GetStatusIRQ() to get the transfer status.
- * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times of the watermark.
- * Otherwise,
- * the last data may be lost because it cannot generate an interrupt request. Users can also call the functional API to
- * get the last
- * received data.
+ * @note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
  *
  * @param base SPI peripheral base address.
  * @param handle pointer to spi_master_handle_t structure which stores the transfer state
@@ -636,20 +641,16 @@ void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
  * @param userData User data.
  */
 void SPI_SlaveTransferCreateHandle(SPI_Type *base,
-                                                 spi_slave_handle_t *handle,
-                                                 spi_slave_callback_t callback,
+                                   spi_slave_handle_t *handle,
+                                   spi_slave_callback_t callback,
                                    void *userData);
 
 /*!
  * @brief Performs a non-blocking SPI slave interrupt transfer.
  *
  * @note The API returns immediately after the transfer initialization is finished.
  * Call SPI_GetStatusIRQ() to get the transfer status.
- * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times the watermark.
- * Otherwise,
- * the last data may be lost because it cannot generate an interrupt request. Call the functional API to get the last
- * several
- * receive data.
+ * @note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
  *
  * @param base SPI peripheral base address.
  * @param handle pointer to spi_master_handle_t structure which stores the transfer state