|
| 1 | +/* |
| 2 | + * mbed Microcontroller Library |
| 3 | + * Copyright (c) 2017-2018 Future Electronics |
| 4 | + * Copyright (c) 2019 Cypress Semiconductor Corporation |
| 5 | + * SPDX-License-Identifier: Apache-2.0 |
| 6 | + * |
| 7 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 8 | + * you may not use this file except in compliance with the License. |
| 9 | + * You may obtain a copy of the License at |
| 10 | + * |
| 11 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 12 | + * |
| 13 | + * Unless required by applicable law or agreed to in writing, software |
| 14 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 15 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 16 | + * See the License for the specific language governing permissions and |
| 17 | + * limitations under the License. |
| 18 | + */ |
| 19 | + |
| 20 | +#ifndef MBED_PERIPHERALNAMES_H |
| 21 | +#define MBED_PERIPHERALNAMES_H |
| 22 | + |
| 23 | +#include "cmsis.h" |
| 24 | +#include "PinNames.h" |
| 25 | + |
| 26 | +#ifdef __cplusplus |
| 27 | +extern "C" { |
| 28 | +#endif |
| 29 | + |
| 30 | +typedef enum { |
| 31 | +#if defined(SCB0_BASE) && (SCB0_UART == 1) |
| 32 | + UART_0 = (int)SCB0_BASE, |
| 33 | +#endif |
| 34 | +#if defined(SCB1_BASE) && (SCB1_UART == 1) |
| 35 | + UART_1 = (int)SCB1_BASE, |
| 36 | +#endif |
| 37 | +#if defined(SCB2_BASE) && (SCB2_UART == 1) |
| 38 | + UART_2 = (int)SCB2_BASE, |
| 39 | +#endif |
| 40 | +#if defined(SCB3_BASE) && (SCB3_UART == 1) |
| 41 | + UART_3 = (int)SCB3_BASE, |
| 42 | +#endif |
| 43 | +#if defined(SCB4_BASE) && (SCB4_UART == 1) |
| 44 | + UART_4 = (int)SCB4_BASE, |
| 45 | +#endif |
| 46 | +#if defined(SCB5_BASE) && (SCB5_UART == 1) |
| 47 | + UART_5 = (int)SCB5_BASE, |
| 48 | +#endif |
| 49 | +#if defined(SCB6_BASE) && (SCB6_UART == 1) |
| 50 | + UART_6 = (int)SCB6_BASE, |
| 51 | +#endif |
| 52 | +#if defined(SCB7_BASE) && (SCB7_UART == 1) |
| 53 | + UART_7 = (int)SCB7_BASE, |
| 54 | +#endif |
| 55 | +#if defined(SCB8_BASE) && (SCB8_UART == 1) |
| 56 | + UART_8 = (int)SCB8_BASE, |
| 57 | +#endif |
| 58 | +#if defined(SCB9_BASE) && (SCB9_UART == 1) |
| 59 | + UART_9 = (int)SCB9_BASE, |
| 60 | +#endif |
| 61 | +#if defined(SCB10_BASE) && (SCB10_UART == 1) |
| 62 | + UART_10 = (int)SCB10_BASE, |
| 63 | +#endif |
| 64 | +#if defined(SCB11_BASE) && (SCB11_UART == 1) |
| 65 | + UART_11 = (int)SCB11_BASE, |
| 66 | +#endif |
| 67 | +#if defined(SCB12_BASE) && (SCB12_UART == 1) |
| 68 | + UART_12 = (int)SCB12_BASE, |
| 69 | +#endif |
| 70 | +} UARTName; |
| 71 | + |
| 72 | +#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES |
| 73 | + |
| 74 | +typedef enum { |
| 75 | +#if defined(SCB0_BASE) && (SCB0_SPI == 1) |
| 76 | + SPI_0 = (int)SCB0_BASE, |
| 77 | +#endif |
| 78 | +#if defined(SCB1_BASE) && (SCB1_SPI == 1) |
| 79 | + SPI_1 = (int)SCB1_BASE, |
| 80 | +#endif |
| 81 | +#if defined(SCB2_BASE) && (SCB2_SPI == 1) |
| 82 | + SPI_2 = (int)SCB2_BASE, |
| 83 | +#endif |
| 84 | +#if defined(SCB3_BASE) && (SCB3_SPI == 1) |
| 85 | + SPI_3 = (int)SCB3_BASE, |
| 86 | +#endif |
| 87 | +#if defined(SCB4_BASE) && (SCB4_SPI == 1) |
| 88 | + SPI_4 = (int)SCB4_BASE, |
| 89 | +#endif |
| 90 | +#if defined(SCB5_BASE) && (SCB5_SPI == 1) |
| 91 | + SPI_5 = (int)SCB5_BASE, |
| 92 | +#endif |
| 93 | +#if defined(SCB6_BASE) && (SCB6_SPI == 1) |
| 94 | + SPI_6 = (int)SCB6_BASE, |
| 95 | +#endif |
| 96 | +#if defined(SCB7_BASE) && (SCB7_SPI == 1) |
| 97 | + SPI_7 = (int)SCB7_BASE, |
| 98 | +#endif |
| 99 | +#if defined(SCB8_BASE) && (SCB8_SPI == 1) |
| 100 | + SPI_8 = (int)SCB8_BASE, |
| 101 | +#endif |
| 102 | +#if defined(SCB9_BASE) && (SCB9_SPI == 1) |
| 103 | + SPI_9 = (int)SCB9_BASE, |
| 104 | +#endif |
| 105 | +#if defined(SCB10_BASE) && (SCB10_SPI == 1) |
| 106 | + SPI_10 = (int)SCB10_BASE, |
| 107 | +#endif |
| 108 | +#if defined(SCB11_BASE) && (SCB11_SPI == 1) |
| 109 | + SPI_11 = (int)SCB11_BASE, |
| 110 | +#endif |
| 111 | +#if defined(SCB12_BASE) && (SCB12_SPI == 1) |
| 112 | + SPI_12 = (int)SCB12_BASE, |
| 113 | +#endif |
| 114 | +} SPIName; |
| 115 | + |
| 116 | +typedef enum { |
| 117 | +#if defined(SCB0_BASE) && (SCB0_I2C == 1) |
| 118 | + I2C_0 = (int)SCB0_BASE, |
| 119 | +#endif |
| 120 | +#if defined(SCB1_BASE) && (SCB1_I2C == 1) |
| 121 | + I2C_1 = (int)SCB1_BASE, |
| 122 | +#endif |
| 123 | +#if defined(SCB2_BASE) && (SCB2_I2C == 1) |
| 124 | + I2C_2 = (int)SCB2_BASE, |
| 125 | +#endif |
| 126 | +#if defined(SCB3_BASE) && (SCB3_I2C == 1) |
| 127 | + I2C_3 = (int)SCB3_BASE, |
| 128 | +#endif |
| 129 | +#if defined(SCB4_BASE) && (SCB4_I2C == 1) |
| 130 | + I2C_4 = (int)SCB4_BASE, |
| 131 | +#endif |
| 132 | +#if defined(SCB5_BASE) && (SCB5_I2C == 1) |
| 133 | + I2C_5 = (int)SCB5_BASE, |
| 134 | +#endif |
| 135 | +#if defined(SCB6_BASE) && (SCB6_I2C == 1) |
| 136 | + I2C_6 = (int)SCB6_BASE, |
| 137 | +#endif |
| 138 | +#if defined(SCB7_BASE) && (SCB7_I2C == 1) |
| 139 | + I2C_7 = (int)SCB7_BASE, |
| 140 | +#endif |
| 141 | +#if defined(SCB8_BASE) && (SCB8_I2C == 1) |
| 142 | + I2C_8 = (int)SCB8_BASE, |
| 143 | +#endif |
| 144 | +#if defined(SCB9_BASE) && (SCB9_I2C == 1) |
| 145 | + I2C_9 = (int)SCB9_BASE, |
| 146 | +#endif |
| 147 | +#if defined(SCB10_BASE) && (SCB10_I2C == 1) |
| 148 | + I2C_10 = (int)SCB10_BASE, |
| 149 | +#endif |
| 150 | +#if defined(SCB11_BASE) && (SCB11_I2C == 1) |
| 151 | + I2C_11 = (int)SCB11_BASE, |
| 152 | +#endif |
| 153 | +#if defined(SCB12_BASE) && (SCB12_I2C == 1) |
| 154 | + I2C_12 = (int)SCB12_BASE, |
| 155 | +#endif |
| 156 | +} I2CName; |
| 157 | + |
| 158 | +typedef enum { |
| 159 | +#ifdef TCPWM0_BASE |
| 160 | +#ifdef TCPWM0_CNT0 |
| 161 | + PWM_32b_0 = TCPWM0_BASE, |
| 162 | +#endif |
| 163 | +#ifdef TCPWM0_CNT1 |
| 164 | + PWM_32b_1, |
| 165 | +#endif |
| 166 | +#ifdef TCPWM0_CNT2 |
| 167 | + PWM_32b_2, |
| 168 | +#endif |
| 169 | +#ifdef TCPWM0_CNT3 |
| 170 | + PWM_32b_3, |
| 171 | +#endif |
| 172 | +#ifdef TCPWM0_CNT4 |
| 173 | + PWM_32b_4, |
| 174 | +#endif |
| 175 | +#ifdef TCPWM0_CNT5 |
| 176 | + PWM_32b_5, |
| 177 | +#endif |
| 178 | +#ifdef TCPWM0_CNT6 |
| 179 | + PWM_32b_6, |
| 180 | +#endif |
| 181 | +#ifdef TCPWM0_CNT7 |
| 182 | + PWM_32b_7, |
| 183 | +#endif |
| 184 | +#endif |
| 185 | +#ifdef TCPWM1_BASE |
| 186 | +#ifdef TCPWM1_CNT0 |
| 187 | + PWM_16b_0 = TCPWM1_BASE, |
| 188 | +#endif |
| 189 | +#ifdef TCPWM1_CNT1 |
| 190 | + PWM_16b_1, |
| 191 | +#endif |
| 192 | +#ifdef TCPWM1_CNT2 |
| 193 | + PWM_16b_2, |
| 194 | +#endif |
| 195 | +#ifdef TCPWM1_CNT3 |
| 196 | + PWM_16b_3, |
| 197 | +#endif |
| 198 | +#ifdef TCPWM1_CNT4 |
| 199 | + PWM_16b_4, |
| 200 | +#endif |
| 201 | +#ifdef TCPWM1_CNT5 |
| 202 | + PWM_16b_5, |
| 203 | +#endif |
| 204 | +#ifdef TCPWM1_CNT6 |
| 205 | + PWM_16b_6, |
| 206 | +#endif |
| 207 | +#ifdef TCPWM1_CNT7 |
| 208 | + PWM_16b_7, |
| 209 | +#endif |
| 210 | +#ifdef TCPWM1_CNT8 |
| 211 | + PWM_16b_8, |
| 212 | +#endif |
| 213 | +#ifdef TCPWM1_CNT9 |
| 214 | + PWM_16b_9, |
| 215 | +#endif |
| 216 | +#ifdef TCPWM1_CNT10 |
| 217 | + PWM_16b_10, |
| 218 | +#endif |
| 219 | +#ifdef TCPWM1_CNT11 |
| 220 | + PWM_16b_11, |
| 221 | +#endif |
| 222 | +#ifdef TCPWM1_CNT12 |
| 223 | + PWM_16b_12, |
| 224 | +#endif |
| 225 | +#ifdef TCPWM1_CNT13 |
| 226 | + PWM_16b_13, |
| 227 | +#endif |
| 228 | +#ifdef TCPWM1_CNT14 |
| 229 | + PWM_16b_14, |
| 230 | +#endif |
| 231 | +#ifdef TCPWM1_CNT15 |
| 232 | + PWM_16b_15, |
| 233 | +#endif |
| 234 | +#ifdef TCPWM1_CNT16 |
| 235 | + PWM_16b_16, |
| 236 | +#endif |
| 237 | +#ifdef TCPWM1_CNT17 |
| 238 | + PWM_16b_17, |
| 239 | +#endif |
| 240 | +#ifdef TCPWM1_CNT18 |
| 241 | + PWM_16b_18, |
| 242 | +#endif |
| 243 | +#ifdef TCPWM1_CNT19 |
| 244 | + PWM_16b_19, |
| 245 | +#endif |
| 246 | +#ifdef TCPWM1_CNT20 |
| 247 | + PWM_16b_20, |
| 248 | +#endif |
| 249 | +#ifdef TCPWM1_CNT21 |
| 250 | + PWM_16b_21, |
| 251 | +#endif |
| 252 | +#ifdef TCPWM1_CNT22 |
| 253 | + PWM_16b_22, |
| 254 | +#endif |
| 255 | +#ifdef TCPWM1_CNT23 |
| 256 | + PWM_16b_23, |
| 257 | +#endif |
| 258 | +#endif |
| 259 | +} PWMName; |
| 260 | + |
| 261 | +#ifdef SAR_BASE |
| 262 | +typedef enum { |
| 263 | + ADC_0 = (int)SAR_BASE, |
| 264 | +} ADCName; |
| 265 | +#endif |
| 266 | + |
| 267 | +#ifdef CTDAC0_BASE |
| 268 | +typedef enum { |
| 269 | + DAC_0 = (int)CTDAC0_BASE, |
| 270 | +} DACName; |
| 271 | +#endif |
| 272 | + |
| 273 | +#ifdef SMIF0_BASE |
| 274 | +typedef enum { |
| 275 | + QSPI_0 = (int)SMIF0_BASE, |
| 276 | +} SMIFName; |
| 277 | +#endif |
| 278 | + |
| 279 | +#ifdef __cplusplus |
| 280 | +} |
| 281 | +#endif |
| 282 | + |
| 283 | +#endif |
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