Merge pull request #5512 from jeromecoutant/PR_L072

 DISCO_L072CZ_LRWAN1 can use LSE from LORA module

Author: theotherjimmy

targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct renamed to targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct

@@ -27,7 +27,7 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
+; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
 LR_IROM1 0x08000000 0x30000  {    ; load region size_region
 
   ER_IROM1 0x08000000 0x30000  {  ; load address = execution address

targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct renamed to targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct

@@ -27,7 +27,7 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
+; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
 LR_IROM1 0x08000000 0x30000  {    ; load region size_region
 
   ER_IROM1 0x08000000 0x30000  {  ; load address = execution address

targets/targets.json

@@ -1570,7 +1570,6 @@
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
-        "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",