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maciejbocianskimaciejbocianski
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qspi_hal_test add DPI and QPI support
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3 files changed

+244
-12
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3 files changed

+244
-12
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‎TESTS/mbed_hal/qspi/flash_configs/N25Q128A_config.h

Lines changed: 112 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@
5858
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
5959
#define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
6060
#define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode
61+
#define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
62+
#define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode
6163

6264
// write operations max time [us] (datasheet max time + 15%)
6365
#define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms
@@ -68,8 +70,10 @@
6870
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
6971
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
7072
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
73+
#define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
7174
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
7275
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
76+
#define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
7377
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
7478

7579

@@ -155,22 +159,122 @@
155159

156160

157161
#define DUAL_ENABLE() \
158-
/* TODO: add implementation */ \
159-
return QSPI_STATUS_OK
162+
\
163+
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
164+
\
165+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
166+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
167+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
168+
return QSPI_STATUS_ERROR; \
169+
} \
170+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
171+
return QSPI_STATUS_ERROR; \
172+
} \
173+
\
174+
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
175+
if (write_register(QSPI_CMD_WRCR2, reg_data, \
176+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
177+
return QSPI_STATUS_ERROR; \
178+
} \
179+
qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
180+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
181+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
182+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
183+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
184+
return QSPI_STATUS_ERROR; \
185+
} \
186+
\
187+
return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
188+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
160189

161190

162191
#define DUAL_DISABLE() \
163-
/* TODO: add implementation */ \
164-
return QSPI_STATUS_OK
192+
\
193+
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
194+
\
195+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
196+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
197+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
198+
return QSPI_STATUS_ERROR; \
199+
} \
200+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
201+
return QSPI_STATUS_ERROR; \
202+
} \
203+
\
204+
reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
205+
if (write_register(QSPI_CMD_WRCR2, reg_data, \
206+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
207+
return QSPI_STATUS_ERROR; \
208+
} \
209+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
210+
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
211+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
212+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
213+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
214+
return QSPI_STATUS_ERROR; \
215+
} \
216+
\
217+
return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
218+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
165219

166220

167221
#define QUAD_ENABLE() \
168-
/* TODO: add implementation */ \
169-
return QSPI_STATUS_OK
222+
\
223+
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
224+
\
225+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
226+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
227+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
228+
return QSPI_STATUS_ERROR; \
229+
} \
230+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
231+
return QSPI_STATUS_ERROR; \
232+
} \
233+
\
234+
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
235+
if (write_register(QSPI_CMD_WRCR2, reg_data, \
236+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
237+
return QSPI_STATUS_ERROR; \
238+
} \
239+
qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
240+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
241+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
242+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
243+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
244+
return QSPI_STATUS_ERROR; \
245+
} \
246+
\
247+
return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
248+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
170249

171250

172251
#define QUAD_DISABLE() \
173-
/* TODO: add implementation */ \
174-
return QSPI_STATUS_OK
252+
\
253+
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
254+
\
255+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
256+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
257+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
258+
return QSPI_STATUS_ERROR; \
259+
} \
260+
if (write_enable(qspi) != QSPI_STATUS_OK) { \
261+
return QSPI_STATUS_ERROR; \
262+
} \
263+
\
264+
reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
265+
if (write_register(QSPI_CMD_WRCR2, reg_data, \
266+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
267+
return QSPI_STATUS_ERROR; \
268+
} \
269+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
270+
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
271+
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
272+
if (read_register(QSPI_CMD_RDCR2, reg_data, \
273+
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
274+
return QSPI_STATUS_ERROR; \
275+
} \
276+
\
277+
return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
278+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
175279

176280
#endif // MBED_QSPI_FLASH_N25Q128A_H

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