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Merge pull request #5847 from SenRamakri/sen_FaultHandler
Unify fault handling and add script to show faults
2 parents e0d79ff + 19ad4e2 commit 84f42f6

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14 files changed

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‎rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S

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;/*
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; * Copyright (c) 2014-2018 ARM Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; *
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; * -----------------------------------------------------------------------------
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; *
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; * Title: Cortex-M Fault Exception handlers ( Common for both ARMv7M and ARMV6M )
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; *
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; * -----------------------------------------------------------------------------
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; */
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#ifndef MBED_FAULT_HANDLER_DISABLED
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#ifndef __DOMAIN_NS
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#define __DOMAIN_NS 1
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#endif
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FAULT_TYPE_HARD_FAULT EQU 0x10
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FAULT_TYPE_MEMMANAGE_FAULT EQU 0x20
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FAULT_TYPE_BUS_FAULT EQU 0x30
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FAULT_TYPE_USAGE_FAULT EQU 0x40
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PRESERVE8
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THUMB
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AREA |.text|, CODE, READONLY
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler
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LDR R3,=FAULT_TYPE_HARD_FAULT
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B Fault_Handler
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler
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LDR R3,=FAULT_TYPE_MEMMANAGE_FAULT
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B Fault_Handler
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler
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LDR R3,=FAULT_TYPE_BUS_FAULT
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B Fault_Handler
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler
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LDR R3,=FAULT_TYPE_USAGE_FAULT
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B Fault_Handler
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ENDP
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Fault_Handler PROC
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EXPORT Fault_Handler
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#if (__DOMAIN_NS == 1)
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IMPORT osRtxInfo
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IMPORT mbed_fault_handler
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IMPORT mbed_fault_context
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MRS R0,MSP
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LDR R1,=0x4
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MOV R2,LR
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TST R2,R1 ; Check EXC_RETURN for bit 2
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BEQ Fault_Handler_Continue
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MRS R0,PSP
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Fault_Handler_Continue
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MOV R12,R3
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LDR R1,=mbed_fault_context
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LDR R2,[R0] ; Capture R0
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#4] ; Capture R1
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#8] ; Capture R2
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#12] ; Capture R3
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STR R2,[R1]
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ADDS R1,#4
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STMIA R1!,{R4-R7} ; Capture R4..R7
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MOV R7,R8 ; Capture R8
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R9 ; Capture R9
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R10 ; Capture R10
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R11 ; Capture R11
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STR R7,[R1]
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ADDS R1,#4
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LDR R2,[R0,#16] ; Capture R12
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STR R2,[R1]
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ADDS R1,#8 ; Add 8 here to capture LR next, we will capture SP later
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LDR R2,[R0,#20] ; Capture LR
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#24] ; Capture PC
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#28] ; Capture xPSR
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STR R2,[R1]
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ADDS R1,#4
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; Adjust stack pointer to its original value and capture it
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MOV R3,R0
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ADDS R3,#0x20 ; Add 0x20 to get the SP value prior to exception
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LDR R6,=0x200
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TST R2,R6 ; Check for if STK was aligned by checking bit-9 in xPSR value
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BEQ Fault_Handler_Continue1
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ADDS R3,#0x4
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Fault_Handler_Continue1
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MOV R5,LR
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LDR R6,=0x10 ; Check for bit-4 to see if FP context was saved
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TST R5,R6
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BNE Fault_Handler_Continue2
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ADDS R3,#0x48 ; 16 FP regs + FPCSR + 1 Reserved
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Fault_Handler_Continue2
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MOV R4,R1
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SUBS R4,#0x10 ; Set the location of SP in ctx
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STR R3,[R4] ; Capture the adjusted SP
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MRS R2,PSP ; Get PSP
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STR R2,[R1]
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ADDS R1,#4
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MRS R2,MSP ; Get MSP
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STR R2,[R1]
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ADDS R1,#4
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LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler
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MOV R0,R12
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LDR R1,=mbed_fault_context
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LDR R2,=osRtxInfo
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BLX R3
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#endif
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B . ; Just in case we come back here
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ENDP
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#endif
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END

‎rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S

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/*
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* Copyright (c) 2014-2018 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Title: Cortex-M Fault Exception handlers ( Common for both ARMv7M and ARMV6M )
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*
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* -----------------------------------------------------------------------------
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*/
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#ifndef MBED_FAULT_HANDLER_DISABLED
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.file "except.S"
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.syntax unified
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#ifndef __DOMAIN_NS
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#define __DOMAIN_NS 1
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#endif
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.equ FAULT_TYPE_HARD_FAULT, 0x10
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.equ FAULT_TYPE_MEMMANAGE_FAULT, 0x20
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.equ FAULT_TYPE_BUS_FAULT, 0x30
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.equ FAULT_TYPE_USAGE_FAULT, 0x40
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.thumb
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.section ".text"
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.align 2
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//HardFault_Handler
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.thumb_func
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.type HardFault_Handler, %function
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.global HardFault_Handler
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.fnstart
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.cantunwind
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HardFault_Handler:
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LDR R3,=FAULT_TYPE_HARD_FAULT
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B Fault_Handler
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.fnend
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.size HardFault_Handler, .-HardFault_Handler
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//MemManage_Handler
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.thumb_func
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.type MemManage_Handler, %function
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.global MemManage_Handler
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.fnstart
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.cantunwind
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MemManage_Handler:
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LDR R3,=FAULT_TYPE_MEMMANAGE_FAULT
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B Fault_Handler
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.fnend
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.size MemManage_Handler, .-MemManage_Handler
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//BusFault_Handler
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.thumb_func
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.type BusFault_Handler, %function
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.global BusFault_Handler
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.fnstart
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.cantunwind
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BusFault_Handler:
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LDR R3,=FAULT_TYPE_BUS_FAULT
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B Fault_Handler
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.fnend
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.size BusFault_Handler, .-BusFault_Handler
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//UsageFault_Handler
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.thumb_func
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.type UsageFault_Handler, %function
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.global UsageFault_Handler
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.fnstart
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.cantunwind
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UsageFault_Handler:
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LDR R3,=FAULT_TYPE_USAGE_FAULT
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B Fault_Handler
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.fnend
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.size UsageFault_Handler, .-UsageFault_Handler
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//Common Fault_Handler to capture the context
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.thumb_func
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.type Fault_Handler, %function
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.global Fault_Handler
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.fnstart
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.cantunwind
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Fault_Handler:
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#if (__DOMAIN_NS == 1)
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MRS R0,MSP
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LDR R1,=0x4
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MOV R2,LR
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TST R2,R1 // Check EXC_RETURN for bit 2
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BEQ Fault_Handler_Continue
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MRS R0,PSP
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Fault_Handler_Continue:
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MOV R12,R3
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LDR R1,=mbed_fault_context
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LDR R2,[R0] // Capture R0
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#4] // Capture R1
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#8] // Capture R2
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#12] // Capture R3
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STR R2,[R1]
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ADDS R1,#4
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STMIA R1!,{R4-R7} // Capture R4..R7
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MOV R7,R8 // Capture R8
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R9 // Capture R9
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R10 // Capture R10
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R11 // Capture R11
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STR R7,[R1]
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ADDS R1,#4
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LDR R2,[R0,#16] // Capture R12
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STR R2,[R1]
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ADDS R1,#8 // Add 8 here to capture LR next, we will capture SP later
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LDR R2,[R0,#20] // Capture LR
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#24] // Capture PC
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#28] // Capture xPSR
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STR R2,[R1]
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ADDS R1,#4
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// Adjust stack pointer to its original value and capture it
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MOV R3,R0
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ADDS R3,#0x20 // Add 0x20 to get the SP value prior to exception
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LDR R6,=0x200
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TST R2,R6 // Check for if STK was aligned by checking bit-9 in xPSR value
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BEQ Fault_Handler_Continue1
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ADDS R3,#0x4
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Fault_Handler_Continue1:
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MOV R5,LR
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LDR R6,=0x10 // Check for bit-4 to see if FP context was saved
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TST R5,R6
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BNE Fault_Handler_Continue2
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ADDS R3,#0x48 // 16 FP regs + FPCSR + 1 Reserved
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Fault_Handler_Continue2:
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MOV R4,R1
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SUBS R4,#0x10 // Set the location of SP in ctx
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STR R3,[R4] // Capture the adjusted SP
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MRS R2,PSP // Get PSP
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STR R2,[R1]
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ADDS R1,#4
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MRS R2,MSP // Get MSP
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STR R2,[R1]
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ADDS R1,#4
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LDR R3,=mbed_fault_handler // Load address of mbedFaultHandler
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MOV R0,R12
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LDR R1,=mbed_fault_context
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LDR R2,=osRtxInfo
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BLX R3
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#endif
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B . // Just in case we come back here
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.fnend
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.size Fault_Handler, .-Fault_Handler
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#endif
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.end
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