Bugfix for EFM32PG12 and EFR32MG12

* Off by one error in the linker scripts reserved one word too little for the vector table
* Re-apply uvisor changes to emlib. To allow uvisor to run, we should make accesses to the romtable through uvisor's secure read gateway
* Copypasta in target name (EFM32PG12, not EFR32PG12)
* Copypasta in the pin definitions (thanks @akselsm)
* Forgot to update PortName for extra ports on MG/PG12

Author: stevew817

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h

@@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20000108 0x0003FEF8  {  ; RW data
+  RW_IRAM1 0x2000010C 0x0003FEF4  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c

@@ -17,8 +17,8 @@ MEMORY
 
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */
-__vector_size = 0x108;
+ * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */
+__vector_size = 0x10C;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h

@@ -10,8 +10,8 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
 define symbol __ICFEDIT_region_ROM_end__     = (0x00000000+0x00100000-1);
 define symbol __NVIC_start__                 = 0x20000000;
-define symbol __NVIC_end__                   = 0x20000107;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000108;
+define symbol __NVIC_end__                   = 0x2000010B;
+define symbol __ICFEDIT_region_RAM_start__   = 0x2000010C;
 define symbol __ICFEDIT_region_RAM_end__     = (0x20000000+0x00040000-1);
 
 /*-Sizes-*/

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h

@@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20000108 0x0003FEF8  {  ; RW data
+  RW_IRAM1 0x2000010C 0x0003FEF4  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h

@@ -17,8 +17,8 @@ MEMORY
 
 /* MBED: mbed needs to be able to dynamically set the interrupt vector table.
  * We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */
-__vector_size = 0x108;
+ * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */
+__vector_size = 0x10C;
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct

@@ -7,8 +7,8 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
 define symbol __ICFEDIT_region_ROM_end__     = 0x000FFFFF;
 define symbol __NVIC_start__                 = 0x20000000;
-define symbol __NVIC_end__                   = 0x20000107;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000108;
+define symbol __NVIC_end__                   = 0x2000010B;
+define symbol __ICFEDIT_region_RAM_start__   = 0x2000010C;
 define symbol __ICFEDIT_region_RAM_end__     = 0x2003FFFF;
 /*-Sizes-*/
 /*Heap 1/4 of ram and stack 1/8*/

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s

@@ -30,17 +30,17 @@
  * bits represent port number (A = 0, B = 1, ...)
  */
 #define EFM32_STANDARD_PIN_DEFINITIONS                                                             \
-    PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \
-    PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \
-    PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \
-    PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \
-    PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \
-    PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \
-    PG0 = 6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \
-    PH0 = 7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \
-    PI0 = 7 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
-    PJ0 = 7 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
-    PK0 = 7 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
+    PA0 =  0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \
+    PB0 =  1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \
+    PC0 =  2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \
+    PD0 =  3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \
+    PE0 =  4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \
+    PF0 =  5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \
+    PG0 =  6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \
+    PH0 =  7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \
+    PI0 =  8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
+    PJ0 =  9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
+    PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
     NC = (int) 0xFFFFFFFF
 
 #ifdef __cplusplus

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld

@@ -46,13 +46,22 @@ typedef enum {
     PortE = gpioPortE, /**< Port E */
 #endif
 #if ( _GPIO_PORT_F_PIN_COUNT > 0 )
-    PortF = gpioPortF /**< Port F */
+    PortF = gpioPortF, /**< Port F */
 #endif
 #if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )
-    PortG = gpioPortG /**< Port F */
+    PortG = gpioPortG, /**< Port G */
 #endif
 #if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )
-    PortH = gpioPortH /**< Port F */
+    PortH = gpioPortH, /**< Port H */
+#endif
+#if defined( _GPIO_PORT_I_PIN_COUNT ) && ( _GPIO_PORT_I_PIN_COUNT > 0 )
+    PortI = gpioPortI, /**< Port I */
+#endif
+#if defined( _GPIO_PORT_J_PIN_COUNT ) && ( _GPIO_PORT_J_PIN_COUNT > 0 )
+    PortJ = gpioPortJ, /**< Port J */
+#endif
+#if defined( _GPIO_PORT_K_PIN_COUNT ) && ( _GPIO_PORT_K_PIN_COUNT > 0 )
+    PortK = gpioPortK, /**< Port K */
 #endif
 } PortName;
 

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S

@@ -33,6 +33,7 @@
 #include "em_system.h"
 #include "em_assert.h"
 #include <stddef.h>
+#include "core_cmSecureAccess.h"
 
 /***************************************************************************//**
  * @addtogroup emlib
@@ -60,20 +61,25 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
   uint8_t tmp;
 
   EFM_ASSERT(rev);
+  
+  uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));		
+  uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));		
+  uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));		
+  uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3));
 
   /* CHIP FAMILY bit [5:2] */
-  tmp  = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);
+  tmp  = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);
   /* CHIP FAMILY bit [1:0] */
-  tmp |=  ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);
+  tmp |=  ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);
   rev->family = tmp;
 
   /* CHIP MAJOR bit [3:0] */
-  rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;
+  rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;
 
   /* CHIP MINOR bit [7:4] */
-  tmp  = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
+  tmp  = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
   /* CHIP MINOR bit [3:0] */
-  tmp |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
+  tmp |=  ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
   rev->minor = tmp;
 }
 

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf renamed to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf

@@ -2336,18 +2336,18 @@
             }
         }
     },
-    "EFM32PG12B500F1024": {
+    "EFM32PG12B500F1024GL125": {
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32PG12", "1024K"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32PG12B500F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
-        "device_name": "EFM32PG12B500F1024",
+        "device_name": "EFM32PG12B500F1024GL125",
         "public": false
     },
     "EFM32PG12_STK3402": {
-        "inherits": ["EFM32PG12B500F1024"],
+        "inherits": ["EFM32PG12B500F1024GL125"],
         "device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "forced_reset_timeout": 2,
         "config": {