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MCUXpresso: Fix ENET driver to enable interrupts after interrupt handlers are set
Signed-off-by: Mahadevan Mahesh <[email protected]>
1 parent 9e24117 commit 89f8fe4

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4 files changed

+163
-116
lines changed

4 files changed

+163
-116
lines changed

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c

Lines changed: 94 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,8 @@
106106
#define ENET_NTOHS(n) __REV16(n)
107107
#define ENET_NTOHL(n) __REV(n)
108108

109+
/* Typedef for interrupt handler. */
110+
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
109111
/*******************************************************************************
110112
* Prototypes
111113
******************************************************************************/
@@ -132,7 +134,18 @@ static void ENET_SetMacController(ENET_Type *base,
132134
const enet_buffer_config_t *bufferConfig,
133135
uint8_t *macAddr,
134136
uint32_t srcClock_Hz);
135-
137+
/*!
138+
* @brief Set ENET handler.
139+
*
140+
* @param base ENET peripheral base address.
141+
* @param handle The ENET handle pointer.
142+
* @param config ENET configuration stucture pointer.
143+
* @param bufferConfig ENET buffer configuration.
144+
*/
145+
static void ENET_SetHandler(ENET_Type *base,
146+
enet_handle_t *handle,
147+
const enet_config_t *config,
148+
const enet_buffer_config_t *bufferConfig);
136149
/*!
137150
* @brief Set ENET MAC transmit buffer descriptors.
138151
*
@@ -226,22 +239,26 @@ static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, en
226239
static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL};
227240

228241
/*! @brief Pointers to enet clocks for each instance. */
229-
const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT] = ENET_CLOCKS;
242+
const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
230243

231244
/*! @brief Pointers to enet transmit IRQ number for each instance. */
232-
const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
245+
static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
233246
/*! @brief Pointers to enet receive IRQ number for each instance. */
234-
const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS;
247+
static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS;
235248
#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
236249
/*! @brief Pointers to enet timestamp IRQ number for each instance. */
237-
const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS;
250+
static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS;
238251
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
239252
/*! @brief Pointers to enet error IRQ number for each instance. */
240-
const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS;
253+
static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS;
241254

242255
/*! @brief Pointers to enet bases for each instance. */
243256
static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
244257

258+
/* ENET ISR for transactional APIs. */
259+
static enet_isr_t s_enetTxIsr;
260+
static enet_isr_t s_enetRxIsr;
261+
static enet_isr_t s_enetErrIsr;
245262
/*******************************************************************************
246263
* Code
247264
******************************************************************************/
@@ -312,26 +329,13 @@ void ENET_Init(ENET_Type *base,
312329
/* Initializes the ENET receive buffer descriptors. */
313330
ENET_SetRxBufferDescriptors(bufferConfig->rxBdStartAddrAlign, bufferConfig->rxBufferAlign,
314331
bufferConfig->rxBuffSizeAlign, bufferConfig->rxBdNumber,
315-
!!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxByteInterrupt)));
332+
!!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)));
316333

317334
/* Initializes the ENET MAC controller. */
318335
ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz);
319336

320-
/* Initialize the handle to zero. */
321-
memset(handle, 0, sizeof(enet_handle_t));
322-
323-
/* Store transfer parameters in handle pointer. */
324-
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
325-
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
326-
handle->rxBdDirty = bufferConfig->rxBdStartAddrAlign;
327-
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
328-
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
329-
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
330-
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
331-
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
332-
333-
/* Save the handle pointer in the global variables. */
334-
s_ENETHandle[instance] = handle;
337+
/* Set all buffers or data in handler for data transmit/receive process. */
338+
ENET_SetHandler(base, handle, config, bufferConfig);
335339
}
336340

337341
void ENET_Deinit(ENET_Type *base)
@@ -355,6 +359,44 @@ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *use
355359
handle->userData = userData;
356360
}
357361

362+
static void ENET_SetHandler(ENET_Type *base,
363+
enet_handle_t *handle,
364+
const enet_config_t *config,
365+
const enet_buffer_config_t *bufferConfig)
366+
{
367+
uint32_t instance = ENET_GetInstance(base);
368+
369+
memset(handle, 0, sizeof(enet_handle_t));
370+
371+
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
372+
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
373+
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
374+
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
375+
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
376+
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
377+
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
378+
379+
/* Save the handle pointer in the global variables. */
380+
s_ENETHandle[instance] = handle;
381+
382+
/* Set the IRQ handler when the interrupt is enabled. */
383+
if (config->interrupt & ENET_TX_INTERRUPT)
384+
{
385+
s_enetTxIsr = ENET_TransmitIRQHandler;
386+
EnableIRQ(s_enetTxIrqId[instance]);
387+
}
388+
if (config->interrupt & ENET_RX_INTERRUPT)
389+
{
390+
s_enetRxIsr = ENET_ReceiveIRQHandler;
391+
EnableIRQ(s_enetRxIrqId[instance]);
392+
}
393+
if (config->interrupt & ENET_ERR_INTERRUPT)
394+
{
395+
s_enetErrIsr = ENET_ErrorIRQHandler;
396+
EnableIRQ(s_enetErrIrqId[instance]);
397+
}
398+
}
399+
358400
static void ENET_SetMacController(ENET_Type *base,
359401
const enet_config_t *config,
360402
const enet_buffer_config_t *bufferConfig,
@@ -452,20 +494,6 @@ static void ENET_SetMacController(ENET_Type *base,
452494

453495
/* Enables Ethernet interrupt and NVIC. */
454496
ENET_EnableInterrupts(base, config->interrupt);
455-
if (config->interrupt & (kENET_RxByteInterrupt | kENET_RxFrameInterrupt))
456-
{
457-
EnableIRQ(s_enetRxIrqId[instance]);
458-
}
459-
if (config->interrupt & (kENET_TxByteInterrupt | kENET_TxFrameInterrupt))
460-
{
461-
EnableIRQ(s_enetTxIrqId[instance]);
462-
}
463-
if (config->interrupt & (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_GraceStopInterrupt | kENET_MiiInterrupt |
464-
kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt |
465-
kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt | kENET_WakeupInterrupt))
466-
{
467-
EnableIRQ(s_enetErrIrqId[instance]);
468-
}
469497

470498
/* ENET control register setting. */
471499
ecr = base->ECR;
@@ -490,10 +518,10 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
490518

491519
for (count = 0; count < txBdNumber; count++)
492520
{
493-
if (txBuffSizeAlign != NULL)
521+
if (txBuffStartAlign != NULL)
494522
{
495-
/* Set data buffer address. */
496-
curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
523+
/* Set data buffer address. */
524+
curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
497525
}
498526
else
499527
{
@@ -517,6 +545,7 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
517545
/* Increase the index. */
518546
curBuffDescrip++;
519547
}
548+
520549
}
521550

522551
static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign,
@@ -564,12 +593,8 @@ static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartA
564593

565594
void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
566595
{
567-
uint32_t rcr;
568-
uint32_t tcr;
569-
570-
rcr = base->RCR;
571-
tcr = base->TCR;
572-
596+
uint32_t rcr = base->RCR;
597+
uint32_t tcr = base->TCR;
573598
/* Sets speed mode. */
574599
if (kENET_MiiSpeed10M == speed)
575600
{
@@ -1274,11 +1299,9 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
12741299

12751300
/* Enables the time stamp interrupt for the master clock on a device. */
12761301
ENET_EnableInterrupts(base, kENET_TsTimerInterrupt);
1277-
EnableIRQ(s_enetTsIrqId[instance]);
1278-
12791302
/* Enables the transmit interrupt to store the transmit frame time-stamp. */
12801303
ENET_EnableInterrupts(base, kENET_TxFrameInterrupt);
1281-
EnableIRQ(s_enetTxIrqId[instance]);
1304+
ENET_DisableInterrupts(base, kENET_TxBufferInterrupt);
12821305

12831306
/* Setting the receive and transmit state for transaction. */
12841307
handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData;
@@ -1292,6 +1315,11 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
12921315
handle->msTimerSecond = 0;
12931316
handle->txBdDirtyTime = handle->txBdBase;
12941317
handle->txBdDirtyStatic = handle->txBdBase;
1318+
1319+
/* Set the IRQ handler when the interrupt is enabled. */
1320+
s_enetTxIsr = ENET_TransmitIRQHandler;
1321+
EnableIRQ(s_enetTsIrqId[instance]);
1322+
EnableIRQ(s_enetTxIrqId[instance]);
12951323
}
12961324

12971325
void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc)
@@ -1591,14 +1619,19 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
15911619
assert(handle);
15921620

15931621
/* Check if the transmit interrupt happen. */
1594-
if ((kENET_TxByteInterrupt | kENET_TxFrameInterrupt) & base->EIR)
1622+
while ((kENET_TxBufferInterrupt | kENET_TxFrameInterrupt) & base->EIR)
15951623
{
1596-
/* Clear the transmit interrupt event. */
1597-
base->EIR = kENET_TxFrameInterrupt | kENET_TxByteInterrupt;
15981624
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1625+
if (base->EIR & kENET_TxFrameInterrupt)
1626+
{
15991627
/* Store the transmit timestamp from the buffer descriptor should be done here. */
16001628
ENET_StoreTxFrameTime(base, handle);
1629+
}
16011630
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
1631+
1632+
/* Clear the transmit interrupt event. */
1633+
base->EIR = kENET_TxFrameInterrupt | kENET_TxBufferInterrupt;
1634+
16021635
/* Callback function. */
16031636
if (handle->callback)
16041637
{
@@ -1612,10 +1645,10 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
16121645
assert(handle);
16131646

16141647
/* Check if the receive interrupt happen. */
1615-
if ((kENET_RxByteInterrupt | kENET_RxFrameInterrupt) & base->EIR)
1648+
while ((kENET_RxBufferInterrupt | kENET_RxFrameInterrupt) & base->EIR)
16161649
{
16171650
/* Clear the transmit interrupt event. */
1618-
base->EIR = kENET_RxFrameInterrupt | kENET_RxByteInterrupt;
1651+
base->EIR = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt;
16191652

16201653
/* Callback function. */
16211654
if (handle->callback)
@@ -1688,26 +1721,24 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
16881721
}
16891722
}
16901723
}
1724+
1725+
void ENET_1588_Timer_IRQHandler(void)
1726+
{
1727+
ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
1728+
}
16911729
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
16921730

16931731
void ENET_Transmit_IRQHandler(void)
16941732
{
1695-
ENET_TransmitIRQHandler(ENET, s_ENETHandle[0]);
1733+
s_enetTxIsr(ENET, s_ENETHandle[0]);
16961734
}
16971735

16981736
void ENET_Receive_IRQHandler(void)
16991737
{
1700-
ENET_ReceiveIRQHandler(ENET, s_ENETHandle[0]);
1738+
s_enetRxIsr(ENET, s_ENETHandle[0]);
17011739
}
17021740

17031741
void ENET_Error_IRQHandler(void)
17041742
{
1705-
ENET_ErrorIRQHandler(ENET, s_ENETHandle[0]);
1706-
}
1707-
1708-
void ENET_1588_Timer_IRQHandler(void)
1709-
{
1710-
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1711-
ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
1712-
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
1743+
s_enetErrIsr(ENET, s_ENETHandle[0]);
17131744
}

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,10 @@
122122
#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
123123
(ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
124124
#endif
125+
#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt)
126+
#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)
127+
#define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \
128+
kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt)
125129

126130
/*! @name Defines the maximum Ethernet frame size. */
127131
/*@{*/
@@ -224,9 +228,9 @@ typedef enum _enet_interrupt_enable
224228
kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */
225229
kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */
226230
kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */
227-
kENET_TxByteInterrupt = ENET_EIR_TXB_MASK, /*!< TX BYTE interrupt source */
231+
kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */
228232
kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */
229-
kENET_RxByteInterrupt = ENET_EIR_RXB_MASK, /*!< RX BYTE interrupt source */
233+
kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */
230234
kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */
231235
kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */
232236
kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */

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