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bcostm0xc0170
bcostm
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0xc0170
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STM32F4 USB: add patch in CubeF4 hal driver
1 parent 5cefd0d commit 8c2a30b

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4 files changed

+307
-25
lines changed

4 files changed

+307
-25
lines changed

‎targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c

Lines changed: 127 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@
106106
* @{
107107
*/
108108
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
109+
static HAL_StatusTypeDef PCD_ReadRxFifo(PCD_HandleTypeDef *hpcd); // MBED PATCH
109110
/**
110111
* @}
111112
*/
@@ -394,6 +395,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
394395
}
395396
}
396397

398+
// MBED PATCH
399+
if (( epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
400+
{
401+
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
402+
}
403+
// MBED PATCH
404+
397405
if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
398406
{
399407
/* Inform the upper layer that a setup packet is available */
@@ -667,27 +675,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
667675
/* Handle RxQLevel Interrupt */
668676
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
669677
{
670-
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
671-
672-
temp = USBx->GRXSTSP;
673-
674-
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
675-
676-
if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
677-
{
678-
if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
679-
{
680-
USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
681-
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
682-
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
683-
}
684-
}
685-
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
686-
{
687-
USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
688-
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
689-
}
690-
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
678+
PCD_ReadRxFifo(hpcd); // MBED PATCH
691679
}
692680

693681
/* Handle SOF Interrupt */
@@ -1131,6 +1119,86 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
11311119
return HAL_OK;
11321120
}
11331121

1122+
// MBED PATCH
1123+
/**
1124+
* @brief Abort a transaction.
1125+
* @param hpcd: PCD handle
1126+
* @param ep_addr: endpoint address
1127+
* @retval HAL status
1128+
*/
1129+
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
1130+
{
1131+
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
1132+
HAL_StatusTypeDef ret = HAL_OK;
1133+
USB_OTG_EPTypeDef *ep;
1134+
1135+
if ((0x80 & ep_addr) == 0x80)
1136+
{
1137+
ep = &hpcd->IN_ep[ep_addr & 0x7F];
1138+
}
1139+
else
1140+
{
1141+
ep = &hpcd->OUT_ep[ep_addr];
1142+
}
1143+
1144+
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
1145+
1146+
ep->num = ep_addr & 0x7F;
1147+
ep->is_in = ((ep_addr & 0x80) == 0x80);
1148+
1149+
USB_EPSetNak(hpcd->Instance, ep);
1150+
1151+
if ((0x80 & ep_addr) == 0x80)
1152+
{
1153+
ret = USB_EPStopXfer(hpcd->Instance , ep);
1154+
if (ret == HAL_OK)
1155+
{
1156+
ret = USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
1157+
}
1158+
}
1159+
else
1160+
{
1161+
/* Set global NAK */
1162+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
1163+
1164+
/* Read all entries from the fifo so global NAK takes effect */
1165+
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
1166+
{
1167+
PCD_ReadRxFifo(hpcd);
1168+
}
1169+
1170+
/* Stop the transfer */
1171+
ret = USB_EPStopXfer(hpcd->Instance , ep);
1172+
if (ret == HAL_BUSY)
1173+
{
1174+
/* If USB_EPStopXfer returns HAL_BUSY then a setup packet
1175+
* arrived after the rx fifo was processed but before USB_EPStopXfer
1176+
* was called. Process the rx fifo one more time to read the
1177+
* setup packet.
1178+
*
1179+
* Note - after the setup packet has been received no further
1180+
* packets will be received over USB. This is because the next
1181+
* phase (data or status) of the control transfer started by
1182+
* the setup packet will be naked until global nak is cleared.
1183+
*/
1184+
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
1185+
{
1186+
PCD_ReadRxFifo(hpcd);
1187+
}
1188+
1189+
ret = USB_EPStopXfer(hpcd->Instance , ep);
1190+
}
1191+
1192+
/* Clear global nak */
1193+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
1194+
}
1195+
1196+
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
1197+
1198+
return ret;
1199+
}
1200+
// MBED PATCH
1201+
11341202
/**
11351203
* @brief Set a STALL condition over an endpoint.
11361204
* @param hpcd PCD handle
@@ -1356,6 +1424,44 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
13561424
return HAL_OK;
13571425
}
13581426

1427+
// MBED PATCH
1428+
/**
1429+
* @brief Process the next RX fifo entry
1430+
* @param hpcd: PCD handle
1431+
* @retval HAL status
1432+
*/
1433+
static HAL_StatusTypeDef PCD_ReadRxFifo(PCD_HandleTypeDef *hpcd)
1434+
{
1435+
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
1436+
USB_OTG_EPTypeDef *ep;
1437+
uint32_t temp = 0;
1438+
1439+
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
1440+
1441+
temp = USBx->GRXSTSP;
1442+
1443+
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
1444+
1445+
if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
1446+
{
1447+
if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
1448+
{
1449+
USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
1450+
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
1451+
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
1452+
}
1453+
}
1454+
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
1455+
{
1456+
USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
1457+
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
1458+
}
1459+
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
1460+
1461+
return HAL_OK;
1462+
}
1463+
// MBED PATCH
1464+
13591465
/**
13601466
* @}
13611467
*/

‎targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
300300
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
301301
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
302302
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
303+
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); // MBED PATCH
303304
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
304305
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
305306
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

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