Fix the value of SystemCoreClock

The OS timer of RZ/A1 uses P0 clock, so until now it has been set the value of P0 clock in SystemCoreClock.
Changed the system clock value to set to SystemCoreClock.
Changed to refer to P0 clock macro instead of SystemCoreClock in OS timer processing.

Author: d-kato

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c

@@ -30,6 +30,7 @@
 #include <MBRZA1LU.h>
 
 #include <cmsis.h>
+#include "mbed_drv_cfg.h"
 
 
 // Define OS TImer interrupt priority
@@ -62,15 +63,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
   // Get CPG.FRQCR[IFC] bits
   clock = (CPG.FRQCR >> 8) & 0x03;
 
-  // Determine Divider 2 output clock by using SystemCoreClock
+  // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
   if (clock == 0x03U) {
-    clock = (SystemCoreClock * 3U);
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U);
   }
   else if (clock == 0x01U) {
-    clock = (SystemCoreClock * 3U)/2U;
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
   }
   else {
-    clock = SystemCoreClock;
+    clock = RENESAS_RZ_A1_P0_CLK;
   }
 
   // Determine tick frequency

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c

@@ -29,6 +29,8 @@
 #include <RZ_A1LU.h>
 #include "RZ_A1_Init.h"
 #include "irq_ctrl.h"
+#include "mbed_drv_cfg.h"
+
 
 #define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
 #define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
@@ -45,7 +47,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = CM1_RENESAS_RZ_A1_P0_CLK;
+uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
 
 /*----------------------------------------------------------------------------
   System Core Clock update function

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h

@@ -34,6 +34,11 @@
 
 #define RENESAS_RZ_A1_P0_CLK   CM1_RENESAS_RZ_A1_P0_CLK
 
+/* Clock Mode 1 */
+/* CLKIN is 48MHz */
+/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
+#define RENESAS_RZ_A1_SYS_CLK  ((CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U)
+
 #define LP_TICKER_MTU2_CH      2
 
 /* flash (W25Q64JV) */

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c

@@ -30,6 +30,7 @@
 #include <MBRZA1H.h>
 
 #include <cmsis.h>
+#include "mbed_drv_cfg.h"
 
 
 // Define OS TImer interrupt priority
@@ -62,15 +63,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
   // Get CPG.FRQCR[IFC] bits
   clock = (CPG.FRQCR >> 8) & 0x03;
 
-  // Determine Divider 2 output clock by using SystemCoreClock
+  // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
   if (clock == 0x03U) {
-    clock = (SystemCoreClock * 3U);
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U);
   }
   else if (clock == 0x01U) {
-    clock = (SystemCoreClock * 3U)/2U;
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
   }
   else {
-    clock = SystemCoreClock;
+    clock = RENESAS_RZ_A1_P0_CLK;
   }
 
   // Determine tick frequency

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c

@@ -29,6 +29,7 @@
 #include <RZ_A1H.h>
 #include "RZ_A1_Init.h"
 #include "irq_ctrl.h"
+#include "mbed_drv_cfg.h"
 
 #define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
 #define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
@@ -45,7 +46,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
+uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
 
 /*----------------------------------------------------------------------------
   System Core Clock update function

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h

@@ -34,6 +34,11 @@
 
 #define RENESAS_RZ_A1_P0_CLK   CM0_RENESAS_RZ_A1_P0_CLK
 
+/* Clock Mode 0 */
+/* CLKIN is between 10MHz and 13.33MHz */
+/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+#define RENESAS_RZ_A1_SYS_CLK  (CM0_RENESAS_RZ_A1_CLKIN * 30U)
+
 #define LP_TICKER_MTU2_CH      3
 
 /* flash (MX25L6433FM2I) */

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c

@@ -30,6 +30,7 @@
 #include <VKRZA1H.h>
 
 #include <cmsis.h>
+#include "mbed_drv_cfg.h"
 
 
 // Define OS TImer interrupt priority
@@ -62,15 +63,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
   // Get CPG.FRQCR[IFC] bits
   clock = (CPG.FRQCR >> 8) & 0x03;
 
-  // Determine Divider 2 output clock by using SystemCoreClock
+  // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
   if (clock == 0x03U) {
-    clock = (SystemCoreClock * 3U);
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U);
   }
   else if (clock == 0x01U) {
-    clock = (SystemCoreClock * 3U)/2U;
+    clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
   }
   else {
-    clock = SystemCoreClock;
+    clock = RENESAS_RZ_A1_P0_CLK;
   }
 
   // Determine tick frequency

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c

@@ -29,6 +29,7 @@
 #include <VK_RZ_A1H.h>
 #include "RZ_A1_Init.h"
 #include "irq_ctrl.h"
+#include "mbed_drv_cfg.h"
 
 #define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
 #define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
@@ -45,7 +46,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
+uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
 
 /*----------------------------------------------------------------------------
   System Core Clock update function

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h

@@ -34,4 +34,9 @@
 
 #define RENESAS_RZ_A1_P0_CLK   CM0_RENESAS_RZ_A1_P0_CLK
 
+/* Clock Mode 0 */
+/* CLKIN is between 10MHz and 13.33MHz */
+/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+#define RENESAS_RZ_A1_SYS_CLK  (CM0_RENESAS_RZ_A1_CLKIN * 30U)
+
 #endif