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oampooampo
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Clean up STM32 USB HAL
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‎libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp

Lines changed: 36 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -63,24 +63,22 @@ USBHAL::USBHAL(void) {
6363
pin_mode(PA_9, OpenDrain);
6464

6565
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
66+
67+
// Enable interrupts
68+
OTG_FS->GREGS.GAHBCFG |= (1 << 0);
6669

67-
OTG_FS->GREGS.GAHBCFG |= (1 << 0); // Set GINTMSK
68-
OTG_FS->GREGS.GINTSTS |= (1 << 4); // RXFLVL
70+
// Turnaround time to maximum value - too small causes packet loss
71+
OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
6972

70-
OTG_FS->GREGS.GUSBCFG |= (0xF << 10); // TRDT to 0xF for 72MHz AHB2
71-
OTG_FS->GREGS.GINTMSK |= (1 << 1) | // Mode mismatch
72-
(1 << 2) | // OTG
73-
(1 << 3) | // SOF
73+
// Unmask global interrupts
74+
OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
7475
(1 << 4) | // RX FIFO not empty
75-
(1 << 10) | // Early suspend
76-
(1 << 11) | // USB suspend
77-
(1 << 12) | // USB reset
78-
(1 << 13); // Enumeration Done
76+
(1 << 12); // USB reset
7977

8078
OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
8179
(1 << 2); // Non-zero-length status OUT handshake
8280

83-
OTG_FS->GREGS.GCCFG |= (1 << 19) | // VBUS sensing
81+
OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
8482
(1 << 16); // Power Up
8583

8684
instance = this;
@@ -100,9 +98,11 @@ void USBHAL::disconnect(void) {
10098
}
10199

102100
void USBHAL::configureDevice(void) {
101+
// Not needed
103102
}
104103

105104
void USBHAL::unconfigureDevice(void) {
105+
// Not needed
106106
}
107107

108108
void USBHAL::setAddress(uint8_t address) {
@@ -140,8 +140,14 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
140140

141141
if (endpoint & 0x1) { // In Endpoint
142142
// Set up the Tx FIFO
143-
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
144-
(bufferEnd << 0);
143+
if (endpoint == EP0IN) {
144+
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
145+
(bufferEnd << 0);
146+
}
147+
else {
148+
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
149+
(bufferEnd << 0);
150+
}
145151
bufferEnd += maxPacket >> 2;
146152

147153
// Set the In EP specific control settings
@@ -197,15 +203,22 @@ void USBHAL::EP0getWriteResult(void) {
197203
}
198204

199205
void USBHAL::EP0stall(void) {
206+
// If we stall the out endpoint here then we have problems transferring
207+
// and setup requests after the (stalled) get device qualifier requests.
208+
// TODO: Find out if this is correct behavior, or whether we are doing
209+
// something else wrong
200210
stallEndpoint(EP0IN);
201211
// stallEndpoint(EP0OUT);
202212
}
203213

204214
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
205215
uint32_t epIndex = endpoint >> 1;
206-
OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = (1 << 29) | // 1 packet per frame
207-
(1 << 19) | // 1 packet
208-
(maximumSize << 0); // Packet size
216+
uint32_t size = (1 << 19) | // 1 packet
217+
(maximumSize << 0); // Packet size
218+
// if (endpoint == EP0OUT) {
219+
size |= (1 << 29); // 1 setup packet
220+
// }
221+
OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
209222
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
210223
(1 << 26); // Clear NAK
211224

@@ -293,30 +306,22 @@ void USBHAL::usbisr(void) {
293306
OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
294307
OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
295308

296-
OTG_FS->DREGS.DAINTMSK = (1 << 0) | // In 0 EP Mask
297-
(1 << 16); // Out 0 EP Mask
298-
OTG_FS->DREGS.DOEPMSK = (1 << 0) | // Transfer complete
299-
(1 << 3); // Setup phase done
300-
OTG_FS->DREGS.DIEPMSK |= (1 << 0);
309+
OTG_FS->DREGS.DIEPMSK = (1 << 0);
301310

302311
bufferEnd = 0;
303312

313+
// Set the receive FIFO size
304314
OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
305315
bufferEnd += rxFifoSize >> 2;
306316

307-
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((MAX_PACKET_SIZE_EP0 >> 2) << 16) |
308-
bufferEnd << 0;
309-
bufferEnd += (MAX_PACKET_SIZE_EP0 >> 2);
310-
OTG_FS->OUTEP_REGS[0].DOEPTSIZ |= (0x3 << 29); // 3 setup packets
317+
// Create the endpoints, and wait for setup packets on out EP0
318+
realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
319+
realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
320+
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
311321

312322
OTG_FS->GREGS.GINTSTS = (1 << 12);
313323
}
314324

315-
if (OTG_FS->GREGS.GINTSTS & (1 << 13)) { // Enumeration done
316-
OTG_FS->INEP_REGS[0].DIEPCTL &= ~(0x3 << 0); // 64 byte packet size
317-
OTG_FS->GREGS.GINTSTS = (1 << 13);
318-
}
319-
320325
if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
321326
uint32_t status = OTG_FS->GREGS.GRXSTSP;
322327

@@ -337,8 +342,7 @@ void USBHAL::usbisr(void) {
337342
if (type == 0x4) {
338343
// Setup complete
339344
EP0setupCallback();
340-
OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 31) |
341-
(1 << 26); // CNAK
345+
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
342346
}
343347

344348
if (type == 0x2) {
@@ -365,8 +369,6 @@ void USBHAL::usbisr(void) {
365369
for (uint32_t i=0; i<4; i++) {
366370
if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
367371

368-
// If the Tx FIFO is empty on EP0 we need to send a further
369-
// packet, so call EP0in()
370372
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
371373
// If the Tx FIFO is empty on EP0 we need to send a further
372374
// packet, so call EP0in()
@@ -394,23 +396,6 @@ void USBHAL::usbisr(void) {
394396
SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
395397
OTG_FS->GREGS.GINTSTS = (1 << 3);
396398
}
397-
398-
if (OTG_FS->GREGS.GINTSTS & (1 << 1)) {
399-
OTG_FS->GREGS.GINTSTS = (1 << 1);
400-
}
401-
402-
if (OTG_FS->GREGS.GINTSTS & (1 << 2)) {
403-
OTG_FS->GREGS.GINTSTS = (1 << 2);
404-
}
405-
406-
if (OTG_FS->GREGS.GINTSTS & (1 << 10)) {
407-
OTG_FS->GREGS.GINTSTS = (1 << 10);
408-
}
409-
410-
if (OTG_FS->GREGS.GINTSTS & (1 << 11)) {
411-
OTG_FS->GREGS.GINTSTS = (1 << 11);
412-
}
413-
414399
}
415400

416401

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