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Commit 8e13f1d

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author
Deepika
committed
Set all peripherals and interrupts as non-secure by default
By default all peripherals will be non-secure in mbed-os and only specific required will be update to secure mode based on requirements
1 parent 508037e commit 8e13f1d

33 files changed

+379
-2078
lines changed

‎targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/PeripheralNames.h

Lines changed: 1 addition & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -68,36 +68,12 @@ typedef enum {
6868
} ADCName;
6969

7070
typedef enum {
71-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<16))
72-
UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0),
73-
#else
7471
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
75-
#endif
76-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<17))
77-
UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0),
78-
#else
7972
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
80-
#endif
81-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<18))
82-
UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0),
83-
#else
8473
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
85-
#endif
86-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<19))
87-
UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0),
88-
#else
8974
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
90-
#endif
91-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<20))
92-
UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0),
93-
#else
9475
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
95-
#endif
96-
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<21))
97-
UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0),
98-
#else
9976
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
100-
#endif
10177
// NOTE: board-specific
10278
STDIO_UART = UART_3
10379
} UARTName;
@@ -152,17 +128,12 @@ typedef enum {
152128
// TIME 0 & TIME 1 only support secure mode
153129
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
154130
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
155-
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (0x01<<17))
156-
TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
157-
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
158-
#else
159131
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
160132
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0),
161-
#endif
162133
} TIMERName;
163134

164135
typedef enum {
165-
RTC_0 = (int) NU_MODNAME(RTC_BASE + NS_OFFSET, 0, 0)
136+
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
166137
} RTCName;
167138

168139
typedef enum {

‎targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/PinNames.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ extern "C" {
3939
#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
4040
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
4141

42-
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) (GPIOA_BASE + NS_OFFSET)) + 0x40 * port)) // Set All GPIO as non-secure
42+
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) (GPIOA_BASE)) + 0x40 * port)) // Set All GPIO as non-secure
4343
#define NU_MFP_POS(pin) ((pin % 8) * 4)
4444
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
4545

‎targets/TARGET_NUVOTON/TARGET_M2351/device/M2351.h

Lines changed: 43 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -31226,15 +31226,30 @@ typedef struct
3122631226
/* Peripheral and SRAM base address */
3122731227
#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
3122831228
#define NS_OFFSET (0x10000000UL)
31229-
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
31229+
31230+
#define PERIPH_BASE_S (0x40000000UL) /*!< (Peripheral) Base Address - Secure */
31231+
#define PERIPH_BASE_NS (0x40000000UL + 0x10000000UL) /*!< (Peripheral) Base Address - Non Secure*/
31232+
31233+
#define AHBPERIPH_BASE_S PERIPH_BASE_S
31234+
#define AHBPERIPH_BASE_NS PERIPH_BASE_NS
31235+
31236+
#define APBPERIPH_BASE_S (PERIPH_BASE_S + 0x00040000)
31237+
#define APBPERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000)
3123031238

3123131239
/* Peripheral memory map */
31232-
#define AHBPERIPH_BASE PERIPH_BASE
31233-
#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
31240+
#if (__DOMAIN_NS == 1U)
31241+
#define PERIPH_BASE PERIPH_BASE_NS /*!< (Peripheral) Base Address - Default */
31242+
#define AHBPERIPH_BASE AHBPERIPH_BASE_NS
31243+
#define APBPERIPH_BASE APBPERIPH_BASE_NS
31244+
#else
31245+
#define PERIPH_BASE PERIPH_BASE_S /*!< (Peripheral) Base Address */
31246+
#define AHBPERIPH_BASE AHBPERIPH_BASE_S
31247+
#define APBPERIPH_BASE APBPERIPH_BASE_S
31248+
#endif
3123431249

3123531250
/*!< AHB peripherals */
31236-
#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
31237-
#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
31251+
#define SYS_BASE (AHBPERIPH_BASE_S + 0x00000)
31252+
#define CLK_BASE (AHBPERIPH_BASE_S + 0x00200)
3123831253
#define INT_BASE (AHBPERIPH_BASE + 0x00300)
3123931254
#define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
3124031255
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
@@ -31246,7 +31261,7 @@ typedef struct
3124631261
#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
3124731262
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
3124831263
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
31249-
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
31264+
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
3125031265
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000)
3125131266
#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000)
3125231267
#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
@@ -31263,14 +31278,20 @@ typedef struct
3126331278
#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
3126431279
#define RTC_BASE (APBPERIPH_BASE + 0x01000)
3126531280
#define EADC_BASE (APBPERIPH_BASE + 0x03000)
31266-
#define EADC0_BASE (APBPERIPH_BASE + 0x03000)
31281+
#define EADC0_BASE (APBPERIPH_BASE + 0x03000)
3126731282
#define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
3126831283
#define DAC0_BASE (APBPERIPH_BASE + 0x07000)
3126931284
#define DAC1_BASE (APBPERIPH_BASE + 0x07040)
3127031285
#define I2S0_BASE (APBPERIPH_BASE + 0x08000)
3127131286
#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
31272-
#define TMR01_BASE (APBPERIPH_BASE + 0x10000)
31287+
31288+
#define TMR01_BASE (APBPERIPH_BASE_S + 0x10000)
31289+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
31290+
#define TMR23_BASE (APBPERIPH_BASE_NS + 0x11000)
31291+
#else
3127331292
#define TMR23_BASE (APBPERIPH_BASE + 0x11000)
31293+
#endif
31294+
3127431295
#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
3127531296
#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
3127631297
#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000)
@@ -31287,7 +31308,13 @@ typedef struct
3128731308
#define UART2_BASE (APBPERIPH_BASE + 0x32000)
3128831309
#define UART3_BASE (APBPERIPH_BASE + 0x33000)
3128931310
#define UART4_BASE (APBPERIPH_BASE + 0x34000)
31290-
#define UART5_BASE (APBPERIPH_BASE + 0x35000)
31311+
31312+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
31313+
#define UART5_BASE (APBPERIPH_BASE_NS + 0x35000)
31314+
#else
31315+
#define UART5_BASE (APBPERIPH_BASE + 0x35000)
31316+
#endif
31317+
3129131318
#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
3129231319
#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
3129331320
#define I2C2_BASE (APBPERIPH_BASE + 0x42000)
@@ -31318,7 +31345,10 @@ typedef struct
3131831345
@{
3131931346
*/
3132031347

31321-
/** @addtogroup PMODULE_S Secure Peripheral Pointer
31348+
#define SYS_S ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */
31349+
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */
31350+
31351+
/** @addtogroup PMODULE_NS Secure Peripheral Pointer
3132231352
The Declaration of Secure Peripheral Pointer
3132331353
@{
3132431354
*/
@@ -31369,23 +31399,19 @@ typedef struct
3136931399

3137031400
#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */
3137131401

31372-
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */
31373-
3137431402
#define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */
3137531403
#define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */
3137631404

3137731405
#define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */
3137831406

31379-
#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */
31380-
3138131407
#define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */
3138231408

3138331409
#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
3138431410

31385-
#define SDH0 ((SDH_T *) SDH0_BASE)
31411+
#define SDH0 ((SDH_T *) SDH0_BASE)
3138631412
#define LCD ((LCD_T *) LCD_BASE)
3138731413

31388-
#define CRPT ((CRPT_T *) CRPT_BASE)
31414+
#define CRPT ((CRPT_T *) CRPT_BASE)
3138931415

3139031416
#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */
3139131417
#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */
@@ -31426,81 +31452,8 @@ typedef struct
3142631452

3142731453
#define DSRC ((DSRC_T *)DSRC_BASE) /*!< DSRC Pointer */
3142831454

31429-
/**@}*/ /* end of group PMODULE_S */
31430-
31431-
/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer
31432-
The Declaration of Non-secure Peripheral Pointer
31433-
@{
31434-
*/
31435-
31436-
31437-
#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */
31438-
#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */
31439-
#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */
31440-
#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */
31441-
#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */
31442-
#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */
31443-
#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */
31444-
#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */
31445-
#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */
31446-
#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */
31447-
#define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */
31448-
#define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */
31449-
#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */
31450-
#define TIMER0_NS ((TIMER_T *) (TMR01_BASE+NS_OFFSET)) /*!< TIMER0 Pointer */
31451-
#define TIMER1_NS ((TIMER_T *) (TMR01_BASE+NS_OFFSET+0x100)) /*!< TIMER1 Pointer */
31452-
#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */
31453-
#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100)) /*!< TIMER3 Pointer */
31454-
#define WDT_NS ((WDT_T *) (WDT_BASE +NS_OFFSET)) /*!< Watch Dog Timer Pointer */
31455-
#define WWDT_NS ((WWDT_T *) (WWDT_BASE+NS_OFFSET)) /*!< Window Watch Dog Timer Pointer */
31456-
#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */
31457-
#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */
31458-
#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */
31459-
#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */
31460-
#define SPI4_NS ((SPI_T *) (SPI4_BASE+NS_OFFSET)) /*!< SPI4 Pointer */
31461-
#define SPI5_NS ((SPI5_T *) (SPI5_BASE+NS_OFFSET)) /*!< SPI5 Pointer */
31462-
#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */
31463-
#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */
31464-
#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
31465-
#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
31466-
#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */
31467-
#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */
31468-
#define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */
31469-
#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */
31470-
#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */
31471-
#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */
31472-
#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */
31473-
#define FMC_NS ((FMC_T *) (FMC_BASE +NS_OFFSET)) /*!< Flash Memory Controller */
31474-
#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET))
31475-
#define LCD_NS ((LCD_T *) (LCD_BASE +NS_OFFSET))
31476-
#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET))
31477-
#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */
31478-
#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */
31479-
#define PWM0_NS ((PWM_T *) (PWM0_BASE +NS_OFFSET)) /*!< PWM0 Pointer */
31480-
#define PWM1_NS ((PWM_T *) (PWM1_BASE +NS_OFFSET)) /*!< PWM1 Pointer */
31481-
#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */
31482-
#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */
31483-
#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */
31484-
#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */
31485-
#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */
31486-
#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */
31487-
#define USBH_NS ((USBH_T *) (USBH_BASE+NS_OFFSET)) /*!< USBH Pointer */
31488-
#define OTG_NS ((OTG_T *) (OTG_BASE+NS_OFFSET)) /*!< OTG Pointer */
31489-
#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */
31490-
#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */
31491-
#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */
31492-
#define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */
31493-
#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */
31494-
#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */
31495-
#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */
31496-
#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */
31497-
#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */
31498-
#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */
31499-
#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */
31500-
#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */
31501-
#define DSRC_NS ((DSRC_T *) (DSRC_BASE+NS_OFFSET)) /*!< DSRC Pointer */
31502-
3150331455
/**@}*/ /* end of group PMODULE_NS */
31456+
3150431457
/**@}*/ /* end of group PMODULE */
3150531458

3150631459
/* -------------------- End of section using anonymous unions ------------------- */

‎targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_bpwm.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_
4040
uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
4141

4242
//clock source is from PCLK
43-
if((bpwm == BPWM0)||(bpwm == BPWM0_NS))
43+
if(bpwm == BPWM0)
4444
u32PWMClockSrc = CLK_GetPCLK0Freq();
4545
else// if((bpwm == BPWM1)||(bpwm == BPWM1_NS))
4646
u32PWMClockSrc = CLK_GetPCLK1Freq();
@@ -94,7 +94,7 @@ uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t
9494
uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
9595

9696
//clock source is from PCLK
97-
if((bpwm == BPWM0)||(bpwm == BPWM0_NS))
97+
if(bpwm == BPWM0)
9898
u32PWMClockSrc = CLK_GetPCLK0Freq();
9999
else// if((bpwm == BPWM1)||(bpwm == BPWM1_NS))
100100
u32PWMClockSrc = CLK_GetPCLK1Freq();

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