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Merge remote-tracking branch 'upstream/master'
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‎libraries/mbed/common/stdio.cpp renamed to ‎libraries/mbed/common/retarget.cpp

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
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#include "FileSystemLike.h"
1919
#include "FilePath.h"
2020
#include "serial_api.h"
21+
#include "toolchain.h"
2122
#include <errno.h>
2223

2324
#if defined(__ARMCC_VERSION)
@@ -386,4 +387,9 @@ namespace __gnu_cxx {
386387
error("Exception");
387388
}
388389
}
390+
extern "C" WEAK void __cxa_pure_virtual(void);
391+
extern "C" WEAK void __cxa_pure_virtual(void) {
392+
exit(1);
393+
}
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389395
#endif

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/cmsis_nvic.c

Lines changed: 6 additions & 5 deletions
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@@ -7,20 +7,21 @@
77

88
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
99
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFFC00) // Vectors positioned at start of RAM
10+
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
1011

1112
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
12-
static volatile uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
13+
uint32_t *vectors = (uint32_t*)SCB->VTOR;
1314
uint32_t i;
1415

1516
// Copy and switch to dynamic vectors if the first time called
16-
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
17-
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
17+
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
18+
uint32_t *old_vectors = vectors;
19+
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
1820
for (i=0; i<NVIC_NUM_VECTORS; i++) {
1921
vectors[i] = old_vectors[i];
2022
}
21-
SCB->VTOR = (uint32_t)vectors;
23+
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
2224
}
23-
2425
vectors[IRQn + 16] = vector;
2526
}
2627

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.c

Lines changed: 9 additions & 8 deletions
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@@ -7,20 +7,21 @@
77

88
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
99
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
10+
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
1011

1112
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
12-
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
13-
int i;
14-
15-
// Copy and switch to dynamic vectors if first time called
16-
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
17-
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
13+
uint32_t *vectors = (uint32_t*)SCB->VTOR;
14+
uint32_t i;
15+
16+
// Copy and switch to dynamic vectors if the first time called
17+
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
18+
uint32_t *old_vectors = vectors;
19+
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
1820
for (i=0; i<NVIC_NUM_VECTORS; i++) {
1921
vectors[i] = old_vectors[i];
2022
}
21-
SCB->VTOR = (uint32_t)vectors;
23+
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
2224
}
23-
2425
vectors[IRQn + 16] = vector;
2526
}
2627

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/LPC11xx.h

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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/LPC1114.sct

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@@ -0,0 +1,14 @@
1+
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LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
3+
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
4+
*.o (RESET, +First)
5+
*(InRoot$$Sections)
6+
.ANY (+RO)
7+
}
8+
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
9+
; 8KB - 0xC0 = 0xF40
10+
RW_IRAM1 0x100000C0 0xF40 {
11+
.ANY (+RW +ZI)
12+
}
13+
}
14+

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s

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1+
;/*****************************************************************************
2+
; * @file: startup_LPC11xx.s
3+
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
4+
; * for the NXP LPC11xx Device Series
5+
; * @version: V1.0
6+
; * @date: 25. Nov. 2008
7+
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
8+
; *
9+
; * Copyright (C) 2008 ARM Limited. All rights reserved.
10+
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
11+
; * processor based microcontrollers. This file can be freely distributed
12+
; * within development tools that are supporting such ARM based processors.
13+
; *
14+
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15+
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16+
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17+
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18+
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
19+
; *
20+
; *****************************************************************************/
21+
22+
Stack_Size EQU 0x00000400
23+
24+
AREA STACK, NOINIT, READWRITE, ALIGN=3
25+
EXPORT __initial_sp
26+
27+
Stack_Mem SPACE Stack_Size
28+
__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
29+
30+
31+
Heap_Size EQU 0x00000000
32+
33+
AREA HEAP, NOINIT, READWRITE, ALIGN=3
34+
EXPORT __heap_base
35+
EXPORT __heap_limit
36+
37+
__heap_base
38+
Heap_Mem SPACE Heap_Size
39+
__heap_limit
40+
41+
PRESERVE8
42+
THUMB
43+
44+
; Vector Table Mapped to Address 0 at Reset
45+
46+
AREA RESET, DATA, READONLY
47+
EXPORT __Vectors
48+
49+
__Vectors DCD __initial_sp ; Top of Stack
50+
DCD Reset_Handler ; Reset Handler
51+
DCD NMI_Handler ; NMI Handler
52+
DCD HardFault_Handler ; Hard Fault Handler
53+
DCD 0 ; Reserved
54+
DCD 0 ; Reserved
55+
DCD 0 ; Reserved
56+
DCD 0 ; Reserved
57+
DCD 0 ; Reserved
58+
DCD 0 ; Reserved
59+
DCD 0 ; Reserved
60+
DCD SVC_Handler ; SVCall Handler
61+
DCD 0 ; Reserved
62+
DCD 0 ; Reserved
63+
DCD PendSV_Handler ; PendSV Handler
64+
DCD SysTick_Handler ; SysTick Handler
65+
66+
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
67+
DCD FLEX_INT1_IRQHandler ;
68+
DCD FLEX_INT2_IRQHandler ;
69+
DCD FLEX_INT3_IRQHandler ;
70+
DCD FLEX_INT4_IRQHandler ;
71+
DCD FLEX_INT5_IRQHandler ;
72+
DCD FLEX_INT6_IRQHandler ;
73+
DCD FLEX_INT7_IRQHandler ;
74+
DCD GINT0_IRQHandler ;
75+
DCD GINT1_IRQHandler ; PIO0 (0:7)
76+
DCD Reserved_IRQHandler ; Reserved
77+
DCD Reserved_IRQHandler ;
78+
DCD Reserved_IRQHandler ;
79+
DCD Reserved_IRQHandler ;
80+
DCD SSP1_IRQHandler ; SSP1
81+
DCD I2C_IRQHandler ; I2C
82+
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
83+
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
84+
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
85+
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
86+
DCD SSP0_IRQHandler ; SSP0
87+
DCD UART_IRQHandler ; UART
88+
DCD USB_IRQHandler ; USB IRQ
89+
DCD USB_FIQHandler ; USB FIQ
90+
DCD ADC_IRQHandler ; A/D Converter
91+
DCD WDT_IRQHandler ; Watchdog timer
92+
DCD BOD_IRQHandler ; Brown Out Detect
93+
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
94+
DCD Reserved_IRQHandler ; Reserved
95+
DCD Reserved_IRQHandler ; Reserved
96+
DCD Reserved_IRQHandler ; Reserved
97+
DCD Reserved_IRQHandler ; Reserved
98+
99+
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
100+
101+
DCD 0xFFFFFFFF ; Datafill
102+
DCD 0xFFFFFFFF ; Datafill
103+
DCD 0xFFFFFFFF ; Datafill
104+
DCD 0xFFFFFFFF ; Datafill
105+
DCD 0xFFFFFFFF ; Datafill
106+
DCD 0xFFFFFFFF ; Datafill
107+
DCD 0xFFFFFFFF ; Datafill
108+
DCD 0xFFFFFFFF ; Datafill
109+
DCD 0xFFFFFFFF ; Datafill
110+
DCD 0xFFFFFFFF ; Datafill
111+
112+
DCD 0xFFFFFFFF ; Datafill
113+
DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
115+
DCD 0xFFFFFFFF ; Datafill
116+
DCD 0xFFFFFFFF ; Datafill
117+
DCD 0xFFFFFFFF ; Datafill
118+
DCD 0xFFFFFFFF ; Datafill
119+
DCD 0xFFFFFFFF ; Datafill
120+
DCD 0xFFFFFFFF ; Datafill
121+
DCD 0xFFFFFFFF ; Datafill
122+
123+
DCD 0xFFFFFFFF ; Datafill
124+
DCD 0xFFFFFFFF ; Datafill
125+
DCD 0xFFFFFFFF ; Datafill
126+
DCD 0xFFFFFFFF ; Datafill
127+
DCD 0xFFFFFFFF ; Datafill
128+
DCD 0xFFFFFFFF ; Datafill
129+
DCD 0xFFFFFFFF ; Datafill
130+
DCD 0xFFFFFFFF ; Datafill
131+
DCD 0xFFFFFFFF ; Datafill
132+
DCD 0xFFFFFFFF ; Datafill
133+
134+
DCD 0xFFFFFFFF ; Datafill
135+
DCD 0xFFFFFFFF ; Datafill
136+
DCD 0xFFFFFFFF ; Datafill
137+
DCD 0xFFFFFFFF ; Datafill
138+
DCD 0xFFFFFFFF ; Datafill
139+
DCD 0xFFFFFFFF ; Datafill
140+
DCD 0xFFFFFFFF ; Datafill
141+
DCD 0xFFFFFFFF ; Datafill
142+
DCD 0xFFFFFFFF ; Datafill
143+
DCD 0xFFFFFFFF ; Datafill
144+
145+
DCD 0xFFFFFFFF ; Datafill
146+
DCD 0xFFFFFFFF ; Datafill
147+
DCD 0xFFFFFFFF ; Datafill
148+
DCD 0xFFFFFFFF ; Datafill
149+
DCD 0xFFFFFFFF ; Datafill
150+
DCD 0xFFFFFFFF ; Datafill
151+
DCD 0xFFFFFFFF ; Datafill
152+
DCD 0xFFFFFFFF ; Datafill
153+
DCD 0xFFFFFFFF ; Datafill
154+
DCD 0xFFFFFFFF ; Datafill
155+
156+
DCD 0xFFFFFFFF ; Datafill
157+
DCD 0xFFFFFFFF ; Datafill
158+
DCD 0xFFFFFFFF ; Datafill
159+
DCD 0xFFFFFFFF ; Datafill
160+
DCD 0xFFFFFFFF ; Datafill
161+
DCD 0xFFFFFFFF ; Datafill
162+
DCD 0xFFFFFFFF ; Datafill
163+
DCD 0xFFFFFFFF ; Datafill
164+
DCD 0xFFFFFFFF ; Datafill
165+
DCD 0xFFFFFFFF ; Datafill
166+
167+
DCD 0xFFFFFFFF ; Datafill
168+
DCD 0xFFFFFFFF ; Datafill
169+
DCD 0xFFFFFFFF ; Datafill
170+
DCD 0xFFFFFFFF ; Datafill
171+
DCD 0xFFFFFFFF ; Datafill
172+
DCD 0xFFFFFFFF ; Datafill
173+
DCD 0xFFFFFFFF ; Datafill
174+
DCD 0xFFFFFFFF ; Datafill
175+
DCD 0xFFFFFFFF ; Datafill
176+
DCD 0xFFFFFFFF ; Datafill
177+
178+
DCD 0xFFFFFFFF ; Datafill
179+
DCD 0xFFFFFFFF ; Datafill
180+
DCD 0xFFFFFFFF ; Datafill
181+
DCD 0xFFFFFFFF ; Datafill
182+
DCD 0xFFFFFFFF ; Datafill
183+
DCD 0xFFFFFFFF ; Datafill
184+
DCD 0xFFFFFFFF ; Datafill
185+
DCD 0xFFFFFFFF ; Datafill
186+
DCD 0xFFFFFFFF ; Datafill
187+
DCD 0xFFFFFFFF ; Datafill
188+
189+
IF :LNOT::DEF:NO_CRP
190+
AREA |.ARM.__at_0x02FC|, CODE, READONLY
191+
CRP_Key DCD 0xFFFFFFFF
192+
ENDIF
193+
194+
195+
AREA |.text|, CODE, READONLY
196+
197+
198+
199+
; Reset Handler
200+
201+
Reset_Handler PROC
202+
EXPORT Reset_Handler [WEAK]
203+
IMPORT SystemInit
204+
IMPORT __main
205+
LDR R0, =SystemInit
206+
BLX R0
207+
LDR R0, =__main
208+
BX R0
209+
ENDP
210+
211+
; Dummy Exception Handlers (infinite loops which can be modified)
212+
213+
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
214+
; for particular peripheral.
215+
;NMI_Handler PROC
216+
; EXPORT NMI_Handler [WEAK]
217+
; B .
218+
; ENDP
219+
HardFault_Handler\
220+
PROC
221+
EXPORT HardFault_Handler [WEAK]
222+
B .
223+
ENDP
224+
SVC_Handler PROC
225+
EXPORT SVC_Handler [WEAK]
226+
B .
227+
ENDP
228+
PendSV_Handler PROC
229+
EXPORT PendSV_Handler [WEAK]
230+
B .
231+
ENDP
232+
SysTick_Handler PROC
233+
EXPORT SysTick_Handler [WEAK]
234+
B .
235+
ENDP
236+
Reserved_IRQHandler PROC
237+
EXPORT Reserved_IRQHandler [WEAK]
238+
B .
239+
ENDP
240+
241+
Default_Handler PROC
242+
; for LPC11Uxx (With USB)
243+
EXPORT NMI_Handler [WEAK]
244+
EXPORT FLEX_INT0_IRQHandler [WEAK]
245+
EXPORT FLEX_INT1_IRQHandler [WEAK]
246+
EXPORT FLEX_INT2_IRQHandler [WEAK]
247+
EXPORT FLEX_INT3_IRQHandler [WEAK]
248+
EXPORT FLEX_INT4_IRQHandler [WEAK]
249+
EXPORT FLEX_INT5_IRQHandler [WEAK]
250+
EXPORT FLEX_INT6_IRQHandler [WEAK]
251+
EXPORT FLEX_INT7_IRQHandler [WEAK]
252+
EXPORT GINT0_IRQHandler [WEAK]
253+
EXPORT GINT1_IRQHandler [WEAK]
254+
EXPORT SSP1_IRQHandler [WEAK]
255+
EXPORT I2C_IRQHandler [WEAK]
256+
EXPORT TIMER16_0_IRQHandler [WEAK]
257+
EXPORT TIMER16_1_IRQHandler [WEAK]
258+
EXPORT TIMER32_0_IRQHandler [WEAK]
259+
EXPORT TIMER32_1_IRQHandler [WEAK]
260+
EXPORT SSP0_IRQHandler [WEAK]
261+
EXPORT UART_IRQHandler [WEAK]
262+
263+
EXPORT USB_IRQHandler [WEAK]
264+
EXPORT USB_FIQHandler [WEAK]
265+
EXPORT ADC_IRQHandler [WEAK]
266+
EXPORT WDT_IRQHandler [WEAK]
267+
EXPORT BOD_IRQHandler [WEAK]
268+
EXPORT FMC_IRQHandler [WEAK]
269+
EXPORT USBWakeup_IRQHandler [WEAK]
270+
271+
NMI_Handler
272+
FLEX_INT0_IRQHandler
273+
FLEX_INT1_IRQHandler
274+
FLEX_INT2_IRQHandler
275+
FLEX_INT3_IRQHandler
276+
FLEX_INT4_IRQHandler
277+
FLEX_INT5_IRQHandler
278+
FLEX_INT6_IRQHandler
279+
FLEX_INT7_IRQHandler
280+
GINT0_IRQHandler
281+
GINT1_IRQHandler
282+
SSP1_IRQHandler
283+
I2C_IRQHandler
284+
TIMER16_0_IRQHandler
285+
TIMER16_1_IRQHandler
286+
TIMER32_0_IRQHandler
287+
TIMER32_1_IRQHandler
288+
SSP0_IRQHandler
289+
UART_IRQHandler
290+
USB_IRQHandler
291+
USB_FIQHandler
292+
ADC_IRQHandler
293+
WDT_IRQHandler
294+
BOD_IRQHandler
295+
FMC_IRQHandler
296+
USBWakeup_IRQHandler
297+
298+
B .
299+
300+
ENDP
301+
302+
ALIGN
303+
END

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