@@ -387,7 +387,7 @@ qspi_status_t qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, uint32_
387
387
static qspi_status_t _qspi_init_direct (qspi_t * obj , const qspi_pinmap_t * pinmap , uint32_t hz , uint8_t mode )
388
388
#endif
389
389
{
390
- tr_info ("qspi_init mode %u" , mode );
390
+ tr_debug ("qspi_init mode %u" , mode );
391
391
392
392
// Reset handle internal state
393
393
obj -> handle .State = HAL_OSPI_STATE_RESET ;
@@ -535,7 +535,7 @@ qspi_status_t qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, uint32_
535
535
static qspi_status_t _qspi_init_direct (qspi_t * obj , const qspi_pinmap_t * pinmap , uint32_t hz , uint8_t mode )
536
536
#endif
537
537
{
538
- tr_info ("qspi_init mode %u" , mode );
538
+ tr_debug ("qspi_init mode %u" , mode );
539
539
// Enable interface clock for QSPI
540
540
__HAL_RCC_QSPI_CLK_ENABLE ();
541
541
@@ -632,7 +632,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN
632
632
#if defined(OCTOSPI1 )
633
633
qspi_status_t qspi_free (qspi_t * obj )
634
634
{
635
- tr_info ("qspi_free" );
635
+ tr_debug ("qspi_free" );
636
636
if (HAL_OSPI_DeInit (& obj -> handle ) != HAL_OK ) {
637
637
return QSPI_STATUS_ERROR ;
638
638
}
@@ -664,7 +664,7 @@ qspi_status_t qspi_free(qspi_t *obj)
664
664
#else /* OCTOSPI */
665
665
qspi_status_t qspi_free (qspi_t * obj )
666
666
{
667
- tr_info ("qspi_free" );
667
+ tr_debug ("qspi_free" );
668
668
669
669
if (HAL_QSPI_DeInit (& obj -> handle ) != HAL_OK ) {
670
670
return QSPI_STATUS_ERROR ;
@@ -701,7 +701,7 @@ qspi_status_t qspi_free(qspi_t *obj)
701
701
#if defined(OCTOSPI1 )
702
702
qspi_status_t qspi_frequency (qspi_t * obj , int hz )
703
703
{
704
- tr_info ("qspi_frequency hz %d" , hz );
704
+ tr_debug ("qspi_frequency hz %d" , hz );
705
705
qspi_status_t status = QSPI_STATUS_OK ;
706
706
707
707
/* HCLK drives QSPI. QSPI clock depends on prescaler value:
@@ -728,7 +728,7 @@ qspi_status_t qspi_frequency(qspi_t *obj, int hz)
728
728
#else /* OCTOSPI */
729
729
qspi_status_t qspi_frequency (qspi_t * obj , int hz )
730
730
{
731
- tr_info ("qspi_frequency hz %d" , hz );
731
+ tr_debug ("qspi_frequency hz %d" , hz );
732
732
qspi_status_t status = QSPI_STATUS_OK ;
733
733
734
734
/* HCLK drives QSPI. QSPI clock depends on prescaler value:
@@ -863,7 +863,7 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data,
863
863
#if defined(OCTOSPI1 )
864
864
qspi_status_t qspi_command_transfer (qspi_t * obj , const qspi_command_t * command , const void * tx_data , size_t tx_size , void * rx_data , size_t rx_size )
865
865
{
866
- tr_info ("qspi_command_transfer tx %u rx %u command %#04x" , tx_size , rx_size , command -> instruction .value );
866
+ tr_debug ("qspi_command_transfer tx %u rx %u command %#04x" , tx_size , rx_size , command -> instruction .value );
867
867
868
868
qspi_status_t status = QSPI_STATUS_OK ;
869
869
@@ -903,7 +903,7 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
903
903
#else /* OCTOSPI */
904
904
qspi_status_t qspi_command_transfer (qspi_t * obj , const qspi_command_t * command , const void * tx_data , size_t tx_size , void * rx_data , size_t rx_size )
905
905
{
906
- tr_info ("qspi_command_transfer tx %u rx %u command %#04x" , tx_size , rx_size , command -> instruction .value );
906
+ tr_debug ("qspi_command_transfer tx %u rx %u command %#04x" , tx_size , rx_size , command -> instruction .value );
907
907
qspi_status_t status = QSPI_STATUS_OK ;
908
908
909
909
if ((tx_data == NULL || tx_size == 0 ) && (rx_data == NULL || rx_size == 0 )) {
0 commit comments