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jeromecoutantjeromecoutant
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STM32F4: remove deprecated macro
1 parent 39d981c commit 927cba8

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38 files changed

+125
-125
lines changed

38 files changed

+125
-125
lines changed

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -837,7 +837,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
837837
/* The voltage scaling allows optimizing the power consumption when the device is
838838
clocked below the maximum system frequency, to update the voltage scaling value
839839
regarding system frequency refer to product datasheet. */
840-
__PWR_CLK_ENABLE();
840+
__HAL_RCC_PWR_CLK_ENABLE();
841841
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
842842

843843
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -896,7 +896,7 @@ uint8_t SetSysClock_PLL_HSI(void)
896896
/* The voltage scaling allows optimizing the power consumption when the device is
897897
clocked below the maximum system frequency, to update the voltage scaling value
898898
regarding system frequency refer to product datasheet. */
899-
__PWR_CLK_ENABLE();
899+
__HAL_RCC_PWR_CLK_ENABLE();
900900
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
901901

902902
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -778,7 +778,7 @@ void SetSysClock(void)
778778
RCC_ClkInitTypeDef RCC_ClkInitStruct;
779779
RCC_OscInitTypeDef RCC_OscInitStruct;
780780

781-
__PWR_CLK_ENABLE();
781+
__HAL_RCC_PWR_CLK_ENABLE();
782782

783783
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
784784

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -842,7 +842,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
842842
/* The voltage scaling allows optimizing the power consumption when the device is
843843
clocked below the maximum system frequency, to update the voltage scaling value
844844
regarding system frequency refer to product datasheet. */
845-
__PWR_CLK_ENABLE();
845+
__HAL_RCC_PWR_CLK_ENABLE();
846846
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
847847

848848
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -899,7 +899,7 @@ uint8_t SetSysClock_PLL_HSI(void)
899899
/* The voltage scaling allows optimizing the power consumption when the device is
900900
clocked below the maximum system frequency, to update the voltage scaling value
901901
regarding system frequency refer to product datasheet. */
902-
__PWR_CLK_ENABLE();
902+
__HAL_RCC_PWR_CLK_ENABLE();
903903
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
904904

905905
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -835,7 +835,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
835835
/* The voltage scaling allows optimizing the power consumption when the device is
836836
clocked below the maximum system frequency, to update the voltage scaling value
837837
regarding system frequency refer to product datasheet. */
838-
__PWR_CLK_ENABLE();
838+
__HAL_RCC_PWR_CLK_ENABLE();
839839
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
840840

841841
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -893,7 +893,7 @@ uint8_t SetSysClock_PLL_HSI(void)
893893
/* The voltage scaling allows optimizing the power consumption when the device is
894894
clocked below the maximum system frequency, to update the voltage scaling value
895895
regarding system frequency refer to product datasheet. */
896-
__PWR_CLK_ENABLE();
896+
__HAL_RCC_PWR_CLK_ENABLE();
897897
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
898898

899899
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -835,7 +835,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
835835
/* The voltage scaling allows optimizing the power consumption when the device is
836836
clocked below the maximum system frequency, to update the voltage scaling value
837837
regarding system frequency refer to product datasheet. */
838-
__PWR_CLK_ENABLE();
838+
__HAL_RCC_PWR_CLK_ENABLE();
839839
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
840840

841841
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -893,7 +893,7 @@ uint8_t SetSysClock_PLL_HSI(void)
893893
/* The voltage scaling allows optimizing the power consumption when the device is
894894
clocked below the maximum system frequency, to update the voltage scaling value
895895
regarding system frequency refer to product datasheet. */
896-
__PWR_CLK_ENABLE();
896+
__HAL_RCC_PWR_CLK_ENABLE();
897897
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
898898

899899
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,7 +1001,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
10011001
/* The voltage scaling allows optimizing the power consumption when the device is
10021002
clocked below the maximum system frequency, to update the voltage scaling value
10031003
regarding system frequency refer to product datasheet. */
1004-
__PWR_CLK_ENABLE();
1004+
__HAL_RCC_PWR_CLK_ENABLE();
10051005
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
10061006

10071007
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -1060,7 +1060,7 @@ uint8_t SetSysClock_PLL_HSI(void)
10601060
/* The voltage scaling allows optimizing the power consumption when the device is
10611061
clocked below the maximum system frequency, to update the voltage scaling value
10621062
regarding system frequency refer to product datasheet. */
1063-
__PWR_CLK_ENABLE();
1063+
__HAL_RCC_PWR_CLK_ENABLE();
10641064
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
10651065

10661066
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,7 +1001,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
10011001
/* The voltage scaling allows optimizing the power consumption when the device is
10021002
clocked below the maximum system frequency, to update the voltage scaling value
10031003
regarding system frequency refer to product datasheet. */
1004-
__PWR_CLK_ENABLE();
1004+
__HAL_RCC_PWR_CLK_ENABLE();
10051005
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
10061006

10071007
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -1060,7 +1060,7 @@ uint8_t SetSysClock_PLL_HSI(void)
10601060
/* The voltage scaling allows optimizing the power consumption when the device is
10611061
clocked below the maximum system frequency, to update the voltage scaling value
10621062
regarding system frequency refer to product datasheet. */
1063-
__PWR_CLK_ENABLE();
1063+
__HAL_RCC_PWR_CLK_ENABLE();
10641064
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
10651065

10661066
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -819,7 +819,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
819819
/* The voltage scaling allows optimizing the power consumption when the device is
820820
clocked below the maximum system frequency, to update the voltage scaling value
821821
regarding system frequency refer to product datasheet. */
822-
__PWR_CLK_ENABLE();
822+
__HAL_RCC_PWR_CLK_ENABLE();
823823
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
824824

825825
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -879,7 +879,7 @@ uint8_t SetSysClock_PLL_HSI(void)
879879
/* The voltage scaling allows optimizing the power consumption when the device is
880880
clocked below the maximum system frequency, to update the voltage scaling value
881881
regarding system frequency refer to product datasheet. */
882-
__PWR_CLK_ENABLE();
882+
__HAL_RCC_PWR_CLK_ENABLE();
883883
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
884884

885885
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -836,7 +836,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
836836
/* The voltage scaling allows optimizing the power consumption when the device is
837837
clocked below the maximum system frequency, to update the voltage scaling value
838838
regarding system frequency refer to product datasheet. */
839-
__PWR_CLK_ENABLE();
839+
__HAL_RCC_PWR_CLK_ENABLE();
840840
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
841841

842842
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -900,7 +900,7 @@ uint8_t SetSysClock_PLL_HSI(void)
900900
/* The voltage scaling allows optimizing the power consumption when the device is
901901
clocked below the maximum system frequency, to update the voltage scaling value
902902
regarding system frequency refer to product datasheet. */
903-
__PWR_CLK_ENABLE();
903+
__HAL_RCC_PWR_CLK_ENABLE();
904904
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
905905

906906
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_stm32f4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -836,7 +836,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
836836
/* The voltage scaling allows optimizing the power consumption when the device is
837837
clocked below the maximum system frequency, to update the voltage scaling value
838838
regarding system frequency refer to product datasheet. */
839-
__PWR_CLK_ENABLE();
839+
__HAL_RCC_PWR_CLK_ENABLE();
840840
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
841841

842842
/* Enable HSE oscillator and activate PLL with HSE as source */
@@ -895,7 +895,7 @@ uint8_t SetSysClock_PLL_HSI(void)
895895
/* The voltage scaling allows optimizing the power consumption when the device is
896896
clocked below the maximum system frequency, to update the voltage scaling value
897897
regarding system frequency refer to product datasheet. */
898-
__PWR_CLK_ENABLE();
898+
__HAL_RCC_PWR_CLK_ENABLE();
899899
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
900900

901901
/* Enable HSI oscillator and activate PLL with HSI as source */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_stm32f4xx.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -870,8 +870,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
870870
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
871871
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
872872
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
873-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
874-
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
873+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
874+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
875875

876876
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
877877

@@ -939,8 +939,8 @@ uint8_t SetSysClock_PLL_HSI(void)
939939
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
940940
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
941941
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
942-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
943-
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
942+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
943+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
944944

945945
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
946946

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -785,7 +785,7 @@ void SetSysClock(void)
785785
RCC_OscInitTypeDef RCC_OscInitStruct;
786786
RCC_ClkInitTypeDef RCC_ClkInitStruct;
787787

788-
__PWR_CLK_ENABLE();
788+
__HAL_RCC_PWR_CLK_ENABLE();
789789

790790
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
791791

@@ -823,7 +823,7 @@ void SetSysClock(void)
823823
RCC_OscInitTypeDef RCC_OscInitStruct;
824824
RCC_ClkInitTypeDef RCC_ClkInitStruct;
825825

826-
__PWR_CLK_ENABLE();
826+
__HAL_RCC_PWR_CLK_ENABLE();
827827

828828
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
829829

@@ -837,7 +837,7 @@ void SetSysClock(void)
837837
RCC_OscInitStruct.PLL.PLLQ = 7;
838838
HAL_RCC_OscConfig(&RCC_OscInitStruct);
839839

840-
HAL_PWREx_ActivateOverDrive();
840+
HAL_PWREx_EnableOverDrive();
841841

842842
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
843843
|RCC_CLOCKTYPE_PCLK2;

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,7 @@ void SetSysClock(void)
786786
RCC_OscInitTypeDef RCC_OscInitStruct;
787787
RCC_ClkInitTypeDef RCC_ClkInitStruct;
788788

789-
__PWR_CLK_ENABLE();
789+
__HAL_RCC_PWR_CLK_ENABLE();
790790

791791
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
792792

@@ -824,7 +824,7 @@ void SetSysClock(void)
824824
RCC_OscInitTypeDef RCC_OscInitStruct;
825825
RCC_ClkInitTypeDef RCC_ClkInitStruct;
826826

827-
__PWR_CLK_ENABLE();
827+
__HAL_RCC_PWR_CLK_ENABLE();
828828

829829
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
830830

@@ -838,7 +838,7 @@ void SetSysClock(void)
838838
RCC_OscInitStruct.PLL.PLLQ = 7;
839839
HAL_RCC_OscConfig(&RCC_OscInitStruct);
840840

841-
HAL_PWREx_ActivateOverDrive();
841+
HAL_PWREx_EnableOverDrive();
842842

843843
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
844844
|RCC_CLOCKTYPE_PCLK2;

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@
4444

4545
#define TIM_MST TIM5
4646
#define TIM_MST_IRQ TIM5_IRQn
47-
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
47+
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
4848

49-
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
50-
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
49+
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
50+
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
5151

5252
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
5353

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