FUTURE_SEQUANA_PSA: fixed deep sleep mode

Enabled tickless mode for Sequana PSA M0 core code to allow it to enter
deep sleep mode. This fixes issue #9094 where tests were failing due to
M0 core not entering deep sleep mode, blocking the whole chip.
Fixed incorrect resource management on M0 core, which crashed tickless
mode.

Author: lrusinowicz

targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/device.h

@@ -67,9 +67,13 @@
  * multiplexer. This requires that we define which of the 32 NVIC channels is used
  * by which interrupt. This is done here.
  */
-#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER    ((IRQn_Type)0)
+#define CY_M0_CORE_IRQ_CHANNEL_LP_TICKER    ((IRQn_Type)0)
+#define CY_M0_CORE_IRQ_CHANNEL_IPC_SYS      ((IRQn_Type)1)
+#define CY_M0_CORE_IRQ_CHANNEL_IPC_USR      ((IRQn_Type)2)
+#define CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX  ((IRQn_Type)3)
 #define CY_M0_CORE_IRQ_CHANNEL_SERIAL       ((IRQn_Type)4)
-#define CY_M0_CORE_IRQ_CHANNEL_BLE          ((IRQn_Type)3)
+#define CY_M0_CORE_IRQ_CHANNEL_BLE          ((IRQn_Type)7)
+#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER    ((IRQn_Type)8)
 
 /** Identifiers used in allocation of NVIC channels.
  */
@@ -78,4 +82,5 @@
 #define CY_BLE_IRQN_ID                      (0x300)
 #define CY_GPIO_IRQN_ID                     (0x400)
 #define CY_LP_TICKER_IRQN_ID                (0x500)
+#define CY_PSA_MAILBOX_IRQN_ID              (0x600)
 #endif

targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_init_api.c

@@ -20,12 +20,13 @@
 
 #include "spm_api.h"
 
-#include "cmsis.h"
+#include "device.h"
 #include "cyip_ipc.h"
 #include "cy_ipc_drv.h"
 #include "cy_syslib.h"
 #include "cy_sysint.h"
-
+#include "psoc6_utils.h"
+#include "mbed_error.h"
 
 
 /* ------------------------------------ Definitions ---------------------------------- */
@@ -65,9 +66,12 @@ void mailbox_init(void)
 
     // Configure interrupts ISR / MUX and priority
     cy_stc_sysint_t ipc_intr_Config;
-    ipc_intr_Config.intrSrc = (IRQn_Type)NvicMux3_IRQn; // Can be any Mux we choose
+    ipc_intr_Config.intrSrc = CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX;
     ipc_intr_Config.cm0pSrc = (cy_en_intr_t)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM0P_INTR;    // Must match the interrupt we trigger using NOTIFY on CM4
     ipc_intr_Config.intrPriority = 1;
+    if (cy_m0_nvic_reserve_channel(CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX, CY_PSA_MAILBOX_IRQN_ID) == (IRQn_Type)(-1)) {
+        error("PSA SPM Mailbox NVIC channel reservation conflict.");
+    }
     (void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);
 
     // Set specific NOTIFY interrupt mask only.