Skip to content

Commit 93e44fb

Browse files
emilmontemilmont
committed
Merge pull request #221 from bcostm/master
[NUCLEO_F302R8] and [NUCLEO_L152RE] updates
2 parents c32258d + 9ac335a commit 93e44fb

File tree

16 files changed

+1023
-283
lines changed

16 files changed

+1023
-283
lines changed

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c

Lines changed: 58 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
* @file system_stm32l1xx.c
44
* @author MCD Application Team
55
* @version V1.2.0
6-
* @date 11-January-2014
6+
* @date 14-March-2014
77
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
88
* This file contains the system clock configuration for STM32L1xx Ultra
99
* Low power devices, and is generated by the clock configuration
@@ -43,29 +43,29 @@
4343
*=============================================================================
4444
* System Clock Configuration
4545
*=============================================================================
46-
* System clock source | HSI
46+
* System Clock source | PLL(HSI)
4747
*-----------------------------------------------------------------------------
48-
* SYSCLK | 16000000 Hz
48+
* SYSCLK | 32000000 Hz
4949
*-----------------------------------------------------------------------------
50-
* HCLK | 16000000 Hz
50+
* HCLK | 32000000 Hz
5151
*-----------------------------------------------------------------------------
5252
* AHB Prescaler | 1
5353
*-----------------------------------------------------------------------------
5454
* APB1 Prescaler | 1
5555
*-----------------------------------------------------------------------------
5656
* APB2 Prescaler | 1
5757
*-----------------------------------------------------------------------------
58-
* HSE Frequency | 8000000 Hz
58+
* HSE Frequency | Not used
5959
*-----------------------------------------------------------------------------
60-
* PLL DIV | Not Used
60+
* PLL DIV | 2
6161
*-----------------------------------------------------------------------------
62-
* PLL MUL | Not Used
62+
* PLL MUL | 4
6363
*-----------------------------------------------------------------------------
6464
* VDD | 3.3 V
6565
*-----------------------------------------------------------------------------
6666
* Vcore | 1.8 V (Range 1)
6767
*-----------------------------------------------------------------------------
68-
* Flash Latency | 0 WS
68+
* Flash Latency | 1 WS
6969
*-----------------------------------------------------------------------------
7070
* Require 48MHz for USB clock | Disabled
7171
*-----------------------------------------------------------------------------
@@ -149,7 +149,7 @@
149149
/** @addtogroup STM32L1xx_System_Private_Variables
150150
* @{
151151
*/
152-
uint32_t SystemCoreClock = 16000000;
152+
uint32_t SystemCoreClock = 32000000;
153153
__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
154154
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
155155

@@ -161,7 +161,7 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
161161
* @{
162162
*/
163163

164-
static void SetSysClock(void);
164+
void SetSysClock(void);
165165

166166
/**
167167
* @}
@@ -206,6 +206,23 @@ void SystemInit (void)
206206
#else
207207
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
208208
#endif
209+
210+
/* ADDED FOR MBED DEBUG PURPOSE */
211+
/*
212+
// Enable the GPIOA peripheral
213+
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
214+
// Output the system clock on MCO pin (PA.08)
215+
GPIO_InitTypeDef GPIO_InitStructure;
216+
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
217+
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
218+
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
219+
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
220+
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
221+
GPIO_Init(GPIOA, &GPIO_InitStructure);
222+
// Select the clock to output on MCO pin (PA.08)
223+
RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCODiv_1);
224+
//RCC_MCOConfig(RCC_MCOSource_HSI, RCC_MCODiv_1);
225+
*/
209226
}
210227

211228
/**
@@ -305,7 +322,7 @@ void SystemCoreClockUpdate (void)
305322
* @param None
306323
* @retval None
307324
*/
308-
static void SetSysClock(void)
325+
void SetSysClock(void)
309326
{
310327
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
311328

@@ -330,42 +347,54 @@ static void SetSysClock(void)
330347

331348
if (HSIStatus == (uint32_t)0x01)
332349
{
333-
/* Flash 0 wait state */
334-
FLASH->ACR &= ~FLASH_ACR_LATENCY;
350+
/* Enable 64-bit access */
351+
FLASH->ACR |= FLASH_ACR_ACC64;
335352

336-
/* Disable Prefetch Buffer */
337-
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
353+
/* Enable Prefetch Buffer */
354+
FLASH->ACR |= FLASH_ACR_PRFTEN;
338355

339-
/* Disable 64-bit access */
340-
FLASH->ACR &= ~FLASH_ACR_ACC64;
356+
/* Flash 1 wait state (latency) */
357+
FLASH->ACR |= FLASH_ACR_LATENCY;
341358

342-
343359
/* Power enable */
344360
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
345361

346362
/* Select the Voltage Range 1 (1.8 V) */
347363
PWR->CR = PWR_CR_VOS_0;
348-
349-
364+
350365
/* Wait Until the Voltage Regulator is ready */
351366
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
352367
{
353368
}
354-
355-
/* HCLK = SYSCLK /1*/
369+
370+
/* PLL configuration */
371+
/* SYSCLK = (HSI 16 MHz * 4) / 2 = 32 MHz */
372+
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV));
373+
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2);
374+
375+
/* HCLK = 32 MHz */
356376
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
357-
/* PCLK2 = HCLK /1*/
377+
378+
/* PCLK2 = 32 MHz */
358379
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
359380

360-
/* PCLK1 = HCLK /1*/
381+
/* PCLK1 = 32 MHz */
361382
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
362-
363-
/* Select HSI as system clock source */
383+
384+
/* Enable PLL */
385+
RCC->CR |= RCC_CR_PLLON;
386+
387+
/* Wait till PLL is ready */
388+
while((RCC->CR & RCC_CR_PLLRDY) == 0)
389+
{
390+
}
391+
392+
/* Select PLL as system clock source */
364393
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
365-
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
394+
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
366395

367-
/* Wait till HSI is used as system clock source */
368-
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
396+
/* Wait till PLL is used as system clock source */
397+
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
369398
{
370399
}
371400
}

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,7 @@ extern "C" {
3737
#endif
3838

3939
typedef enum {
40-
ADC_1 = (int)ADC1_BASE,
41-
ADC_2 = (int)ADC_BASE
40+
ADC_1 = (int)ADC1_BASE
4241
} ADCName;
4342

4443
typedef enum {
@@ -69,9 +68,13 @@ typedef enum {
6968
} I2CName;
7069

7170
typedef enum {
72-
PWM_2 = (int)TIM2_BASE,
73-
PWM_3 = (int)TIM3_BASE,
74-
PWM_4 = (int)TIM4_BASE
71+
PWM_2 = (int)TIM2_BASE,
72+
PWM_3 = (int)TIM3_BASE,
73+
PWM_4 = (int)TIM4_BASE,
74+
PWM_5 = (int)TIM5_BASE,
75+
PWM_9 = (int)TIM9_BASE,
76+
PWM_10 = (int)TIM10_BASE,
77+
PWM_11 = (int)TIM11_BASE
7578
} PWMName;
7679

7780
#ifdef __cplusplus

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,8 @@ typedef enum {
143143
LED3 = PA_5,
144144
LED4 = PA_5,
145145
USER_BUTTON = PC_13,
146+
SERIAL_TX = PA_2,
147+
SERIAL_RX = PA_3,
146148
USBTX = PA_2,
147149
USBRX = PA_3,
148150
I2C_SCL = PB_8,

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c

Lines changed: 75 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -35,23 +35,36 @@
3535
#include "error.h"
3636

3737
static const PinMap PinMap_ADC[] = {
38-
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
39-
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
40-
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
41-
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
42-
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
43-
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
44-
{NC, NC, 0}
38+
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
39+
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
40+
{PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN2
41+
{PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN3
42+
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
43+
{PA_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN5
44+
{PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN6
45+
{PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN7
46+
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
47+
{PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN9
48+
{PB_12, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN18
49+
{PB_13, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN19
50+
{PB_14, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN20
51+
{PB_15, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN21
52+
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
53+
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
54+
{PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN12
55+
{PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN13
56+
{PC_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN14
57+
{PC_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN15
58+
{NC, NC, 0}
4559
};
4660

4761
int adc_inited = 0;
4862

4963
void analogin_init(analogin_t *obj, PinName pin) {
50-
51-
ADC_TypeDef *adc;
64+
ADC_TypeDef *adc;
5265
ADC_InitTypeDef ADC_InitStructure;
5366

54-
// Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
67+
// Get the peripheral name from the pin and assign it to the object
5568
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
5669

5770
if (obj->adc == (ADCName)NC) {
@@ -92,31 +105,76 @@ void analogin_init(analogin_t *obj, PinName pin) {
92105
static inline uint16_t adc_read(analogin_t *obj) {
93106
// Get ADC registers structure address
94107
ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
108+
uint8_t channel = 0;
95109

96110
// Configure ADC channel
97111
switch (obj->pin) {
98112
case PA_0:
99-
ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_4Cycles);
113+
channel = ADC_Channel_0;
100114
break;
101115
case PA_1:
102-
ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_4Cycles);
116+
channel = ADC_Channel_1;
117+
break;
118+
case PA_2:
119+
channel = ADC_Channel_2;
103120
break;
121+
case PA_3:
122+
channel = ADC_Channel_3;
123+
break;
104124
case PA_4:
105-
ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_4Cycles);
125+
channel = ADC_Channel_4;
126+
break;
127+
case PA_5:
128+
channel = ADC_Channel_5;
129+
break;
130+
case PA_6:
131+
channel = ADC_Channel_6;
106132
break;
133+
case PA_7:
134+
channel = ADC_Channel_7;
135+
break;
107136
case PB_0:
108-
ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_4Cycles);
137+
channel = ADC_Channel_8;
109138
break;
110-
case PC_1:
111-
ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_4Cycles);
139+
case PB_1:
140+
channel = ADC_Channel_9;
141+
break;
142+
case PB_12:
143+
channel = ADC_Channel_18;
144+
break;
145+
case PB_13:
146+
channel = ADC_Channel_19;
112147
break;
148+
case PB_14:
149+
channel = ADC_Channel_20;
150+
break;
151+
case PB_15:
152+
channel = ADC_Channel_21;
153+
break;
113154
case PC_0:
114-
ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_4Cycles);
155+
channel = ADC_Channel_10;
156+
break;
157+
case PC_1:
158+
channel = ADC_Channel_11;
159+
break;
160+
case PC_2:
161+
channel = ADC_Channel_12;
115162
break;
163+
case PC_3:
164+
channel = ADC_Channel_13;
165+
break;
166+
case PC_4:
167+
channel = ADC_Channel_14;
168+
break;
169+
case PC_5:
170+
channel = ADC_Channel_15;
171+
break;
116172
default:
117173
return 0;
118174
}
119175

176+
ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_4Cycles);
177+
120178
ADC_SoftwareStartConv(adc); // Start conversion
121179

122180
while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion

0 commit comments

Comments
 (0)