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Change LPC54608 to LPC546XX to include support for LPC54608/18/28
Signed-off-by: Mahadevan Mahesh <[email protected]>
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‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a

-21.6 KB
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‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a

-9.63 KB
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‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,11 @@
4545
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
4646
!!ClocksProfile
4747
product: Clocks v1.0
48-
processor: LPC54608J512
49-
package_id: LPC54608J512ET180
48+
processor: LPC54618J512
49+
package_id: LPC54618J512ET180
5050
mcu_data: ksdk2_0
5151
processor_version: 0.0.0
52-
board: LPCXpresso54608
52+
board: LPCXpresso54618
5353
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
5454

5555
#include "fsl_power.h"

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h

Lines changed: 50 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
** ###################################################################
3-
** Processors: LPC54608J512BD208
4-
** LPC54608J512ET180
3+
** Processors: LPC54618J512BD208
4+
** LPC54618J512ET180
55
**
66
** Compilers: Keil ARM C/C++ Compiler
77
** GNU C Compiler
@@ -13,7 +13,7 @@
1313
** Build: b170214
1414
**
1515
** Abstract:
16-
** CMSIS Peripheral Access Layer for LPC54608
16+
** CMSIS Peripheral Access Layer for LPC54618
1717
**
1818
** Copyright 1997-2016 Freescale Semiconductor, Inc.
1919
** Copyright 2016-2017 NXP
@@ -56,16 +56,16 @@
5656
*/
5757

5858
/*!
59-
* @file LPC54608.h
59+
* @file LPC54618.h
6060
* @version 1.1
6161
* @date 2016-11-25
62-
* @brief CMSIS Peripheral Access Layer for LPC54608
62+
* @brief CMSIS Peripheral Access Layer for LPC54618
6363
*
64-
* CMSIS Peripheral Access Layer for LPC54608
64+
* CMSIS Peripheral Access Layer for LPC54618
6565
*/
6666

67-
#ifndef _LPC54608_H_
68-
#define _LPC54608_H_ /**< Symbol preventing repeated inclusion */
67+
#ifndef _LPC54618_H_
68+
#define _LPC54618_H_ /**< Symbol preventing repeated inclusion */
6969

7070
/** Memory map major version (memory maps with equal major version number are
7171
* compatible) */
@@ -181,7 +181,7 @@ typedef enum IRQn {
181181
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
182182

183183
#include "core_cm4.h" /* Core Peripheral Access Layer */
184-
#include "system_LPC54608.h" /* Device specific configuration file */
184+
#include "system_LPC54618.h" /* Device specific configuration file */
185185

186186
/*!
187187
* @}
@@ -713,7 +713,8 @@ typedef struct {
713713

714714
/** CAN - Register Layout Typedef */
715715
typedef struct {
716-
uint8_t RESERVED_0[16];
716+
uint8_t RESERVED_0[12];
717+
__IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
717718
__IO uint32_t TEST; /**< Test Register, offset: 0x10 */
718719
uint8_t RESERVED_1[4];
719720
__IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
@@ -779,6 +780,23 @@ typedef struct {
779780
* @{
780781
*/
781782

783+
/*! @name DBTP - Data Bit Timing Prescaler Register */
784+
#define CAN_DBTP_DSJW_MASK (0xFU)
785+
#define CAN_DBTP_DSJW_SHIFT (0U)
786+
#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
787+
#define CAN_DBTP_DTSEG2_MASK (0xF0U)
788+
#define CAN_DBTP_DTSEG2_SHIFT (4U)
789+
#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
790+
#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
791+
#define CAN_DBTP_DTSEG1_SHIFT (8U)
792+
#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
793+
#define CAN_DBTP_DBRP_MASK (0x1F0000U)
794+
#define CAN_DBTP_DBRP_SHIFT (16U)
795+
#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
796+
#define CAN_DBTP_TDC_MASK (0x800000U)
797+
#define CAN_DBTP_TDC_SHIFT (23U)
798+
#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
799+
782800
/*! @name TEST - Test Register */
783801
#define CAN_TEST_LBCK_MASK (0x10U)
784802
#define CAN_TEST_LBCK_SHIFT (4U)
@@ -815,6 +833,12 @@ typedef struct {
815833
#define CAN_CCCR_TEST_MASK (0x80U)
816834
#define CAN_CCCR_TEST_SHIFT (7U)
817835
#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
836+
#define CAN_CCCR_FDOE_MASK (0x100U)
837+
#define CAN_CCCR_FDOE_SHIFT (8U)
838+
#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
839+
#define CAN_CCCR_BRSE_MASK (0x200U)
840+
#define CAN_CCCR_BRSE_SHIFT (9U)
841+
#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
818842
#define CAN_CCCR_PXHD_MASK (0x1000U)
819843
#define CAN_CCCR_PXHD_SHIFT (12U)
820844
#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
@@ -824,6 +848,9 @@ typedef struct {
824848
#define CAN_CCCR_TXP_MASK (0x4000U)
825849
#define CAN_CCCR_TXP_SHIFT (14U)
826850
#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
851+
#define CAN_CCCR_NISO_MASK (0x8000U)
852+
#define CAN_CCCR_NISO_SHIFT (15U)
853+
#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
827854

828855
/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
829856
#define CAN_NBTP_NTSEG2_MASK (0x7FU)
@@ -898,6 +925,18 @@ typedef struct {
898925
#define CAN_PSR_BO_MASK (0x80U)
899926
#define CAN_PSR_BO_SHIFT (7U)
900927
#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
928+
#define CAN_PSR_DLEC_MASK (0x700U)
929+
#define CAN_PSR_DLEC_SHIFT (8U)
930+
#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
931+
#define CAN_PSR_RESI_MASK (0x800U)
932+
#define CAN_PSR_RESI_SHIFT (11U)
933+
#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
934+
#define CAN_PSR_RBRS_MASK (0x1000U)
935+
#define CAN_PSR_RBRS_SHIFT (12U)
936+
#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
937+
#define CAN_PSR_RFDF_MASK (0x2000U)
938+
#define CAN_PSR_RFDF_SHIFT (13U)
939+
#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
901940
#define CAN_PSR_PXE_MASK (0x4000U)
902941
#define CAN_PSR_PXE_SHIFT (14U)
903942
#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
@@ -12367,5 +12406,5 @@ typedef struct {
1236712406
*/ /* end of group SDK_Compatibility_Symbols */
1236812407

1236912408

12370-
#endif /* _LPC54608_H_ */
12409+
#endif /* _LPC54618_H_ */
1237112410

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,8 @@
4646
** ###################################################################
4747
*/
4848

49-
#ifndef _LPC54608_FEATURES_H_
50-
#define _LPC54608_FEATURES_H_
49+
#ifndef _LPC54618_FEATURES_H_
50+
#define _LPC54618_FEATURES_H_
5151

5252
/* SOC module features */
5353

@@ -133,7 +133,7 @@
133133
/* CAN module features */
134134

135135
/* @brief Support CANFD or not */
136-
#define FSL_FEATURE_CAN_SUPPORT_CANFD (0)
136+
#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
137137

138138
/* DMA module features */
139139

@@ -227,5 +227,5 @@
227227
/* @brief Base address of the USB dedicated RAM */
228228
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
229229

230-
#endif /* _LPC54608_FEATURES_H_ */
230+
#endif /* _LPC54618_FEATURES_H_ */
231231

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
#! armcc -E
22
/*
33
** ###################################################################
4-
** Processors: LPC54608J512BD208
5-
** LPC54608J512ET180
4+
** Processors: LPC54618J512BD208
5+
** LPC54618J512ET180
66
**
77
** Compiler: Keil ARM C/C++ Compiler
88
** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar

10.6 KB
Binary file not shown.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
;/*****************************************************************************
2-
; * @file: startup_LPC54608.s
2+
; * @file: startup_LPC54618.s
33
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
4-
; * LPC54608
4+
; * LPC54618
55
; * @version: 1.1
66
; * @date: 2016-11-25
77
; *

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld

Lines changed: 7 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1,61 +1,28 @@
11
/*
22
** ###################################################################
3-
** Processors: LPC54608J512
3+
** Processors: LPC54618J512
44
**
55
** Compiler: GNU C Compiler
6-
** Reference manual: LPC54608 Series Reference Manual, Rev. 0 , 06/2017
6+
** Reference manual: LPC54618 Series Reference Manual, Rev. 0 , 06/2017
77
** Version: rev. 1.0, 2017-6-06
88
** Build: b161214
99
**
1010
** Abstract:
1111
** Linker file for the GNU C Compiler
1212
**
13-
** Copyright (c) 2016 Freescale Semiconductor, Inc.
14-
** Copyright (c) 2016 - 2017 , NXP
15-
** All rights reserved.
16-
**
13+
** Copyright 2016 Freescale Semiconductor, Inc.
14+
** Copyright 2016-2017 NXP
1715
** Redistribution and use in source and binary forms, with or without modification,
1816
** are permitted provided that the following conditions are met:
1917
**
20-
** o Redistributions of source code must retain the above copyright notice, this list
18+
** 1. Redistributions of source code must retain the above copyright notice, this list
2119
** of conditions and the following disclaimer.
2220
**
23-
** o Redistributions in binary form must reproduce the above copyright notice, this
21+
** 2. Redistributions in binary form must reproduce the above copyright notice, this
2422
** list of conditions and the following disclaimer in the documentation and/or
2523
** other materials provided with the distribution.
2624
**
27-
** o Neither the name of copyright holder nor the names of its
28-
** contributors may be used to endorse or promote products derived from this
29-
** software without specific prior written permission.
30-
**
31-
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32-
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33-
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34-
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
35-
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36-
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37-
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
38-
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39-
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40-
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41-
**
42-
** http: www.freescale.com
43-
** mail: [email protected]
44-
**
45-
** Copyright (c) 2016 NXP Semiconductors, Inc.
46-
** All rights reserved.
47-
**
48-
** Redistribution and use in source and binary forms, with or without modification,
49-
** are permitted provided that the following conditions are met:
50-
**
51-
** o Redistributions of source code must retain the above copyright notice, this list
52-
** of conditions and the following disclaimer.
53-
**
54-
** o Redistributions in binary form must reproduce the above copyright notice, this
55-
** list of conditions and the following disclaimer in the documentation and/or
56-
** other materials provided with the distribution.
57-
**
58-
** o Neither the name of NXP Semiconductors, Inc. nor the names of its
25+
** 3. Neither the name of the copyright holder nor the names of its
5926
** contributors may be used to endorse or promote products derived from this
6027
** software without specific prior written permission.
6128
**
@@ -97,8 +64,6 @@ MEMORY
9764
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000
9865
m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000
9966
m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000
100-
101-
10267
}
10368

10469
/* Define output sections */

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a

21.7 KB
Binary file not shown.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S

Lines changed: 7 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,54 +1,25 @@
11
/* ---------------------------------------------------------------------------------------*/
2-
/* @file: startup_LPC54608.S */
2+
/* @file: startup_LPC54618.S */
33
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
4-
/* LPC54608 */
4+
/* LPC54618 */
55
/* @version: 1.0 */
66
/* @date: 2017-6-6 */
77
/* @build: b161214 */
88
/* ---------------------------------------------------------------------------------------*/
99
/* */
10-
/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
11-
/* Copyright (c) 2016 - 2017 , NXP */
12-
/* */
13-
/* Redistribution and use in source and binary forms, with or without modification, */
14-
/* are permitted provided that the following conditions are met: */
15-
/* */
16-
/* o Redistributions of source code must retain the above copyright notice, this list */
17-
/* of conditions and the following disclaimer. */
18-
/* */
19-
/* o Redistributions in binary form must reproduce the above copyright notice, this */
20-
/* list of conditions and the following disclaimer in the documentation and/or */
21-
/* other materials provided with the distribution. */
22-
/* */
23-
/* o Neither the name of copyright holder nor the names of its */
24-
/* contributors may be used to endorse or promote products derived from this */
25-
/* software without specific prior written permission. */
26-
/* */
27-
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
28-
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
29-
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
30-
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
31-
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
32-
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
33-
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
34-
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
35-
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
36-
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
37-
/* */
38-
/* Copyright (c) 2016 , NXP Semiconductors, Inc. */
39-
/* All rights reserved. */
40-
/* */
10+
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
11+
/* Copyright 2016-2017 NXP */
4112
/* Redistribution and use in source and binary forms, with or without modification, */
4213
/* are permitted provided that the following conditions are met: */
4314
/* */
44-
/* o Redistributions of source code must retain the above copyright notice, this list */
15+
/* 1. Redistributions of source code must retain the above copyright notice, this list */
4516
/* of conditions and the following disclaimer. */
4617
/* */
47-
/* o Redistributions in binary form must reproduce the above copyright notice, this */
18+
/* 2. Redistributions in binary form must reproduce the above copyright notice, this */
4819
/* list of conditions and the following disclaimer in the documentation and/or */
4920
/* other materials provided with the distribution. */
5021
/* */
51-
/* o Neither the name of NXP Semiconductors, Inc. nor the names of its */
22+
/* 3. Neither the name of the copyright holder nor the names of its */
5223
/* contributors may be used to endorse or promote products derived from this */
5324
/* software without specific prior written permission. */
5425
/* */

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
** ###################################################################
3-
** Processors: LPC54608J512BD208
4-
** LPC54608J512ET180
3+
** Processors: LPC54618J512BD208
4+
** LPC54618J512ET180
55
**
66
** Compiler: IAR ANSI C/C++ Compiler for ARM
77
** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a

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‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S

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@@ -1,7 +1,7 @@
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;/*****************************************************************************
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; * @file: startup_LPC54608.s
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; * @file: startup_LPC54618.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File
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; * LPC54608
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; * LPC54618
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; * @version: 1.1
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; * @date: 2016-11-25
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; *----------------------------------------------------------------------------

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis_nvic.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h

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*
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* The CPU macro should be declared in the project or makefile.
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*/
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#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180))
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#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180))
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#define LPC54608_SERIES
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#define LPC54618_SERIES
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/* CMSIS-style register definitions */
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#include "LPC54608.h"
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#include "LPC54618.h"
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/* CPU specific feature definitions */
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#include "LPC54608_features.h"
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#include "LPC54618_features.h"
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#else
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#error "No valid CPU defined!"

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