Merge pull request #5025 from grygorek/master

LPC1769 port

Author: adbridge

features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c

@@ -63,6 +63,12 @@
  * @{
  */
 
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC1769)
+/** \brief Group LPC17xx processors into one definition
+ */
+#define TARGET_LPC17XX
+#endif
+
 #if NO_SYS == 0
 /** \brief  Driver transmit and receive thread priorities
  *
@@ -146,7 +152,7 @@ struct lpc_enetdata {
 #  else
 #     define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
 #  endif
-#elif defined(TARGET_LPC1768)
+#elif defined(TARGET_LPC17XX)
 #  if defined(TOOLCHAIN_GCC_ARM)
 #     define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
 #  endif
@@ -370,7 +376,7 @@ static struct pbuf *lpc_low_level_input(struct netif *netif)
     			LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
                     ("lpc_low_level_input: Packet index %"U32_F" dropped for OOM\n",
     				idx));
-			
+
 #ifdef LOCK_RX_THREAD
 #if NO_SYS == 0
         		sys_mutex_unlock(&lpc_enetif->TXLockMutex);
@@ -428,7 +434,7 @@ void lpc_enetif_input(struct netif *netif)
  */
 static s32_t lpc_packet_addr_notsafe(void *addr) {
 	/* Check for legal address ranges */
-#if defined(TARGET_LPC1768)
+#if defined(TARGET_LPC17XX)
 	if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
 	if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
@@ -790,7 +796,7 @@ static err_t low_level_init(struct netif *netif)
 	/* Enable MII clocking */
 	LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
 
-#if defined(TARGET_LPC1768)
+#if defined(TARGET_LPC17XX)
 	LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
 	LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)

targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h

@@ -55,6 +55,32 @@ typedef enum {
     p18 = P0_26,
     p19 = P1_30,
     p20 = P1_31,
+#if defined(TARGET_LPC1769)
+    p21 = P0_2,
+    p22 = P0_3,
+    p23 = P0_21,
+    p24 = P0_22,
+    p25 = P0_27,
+    p26 = P0_28,
+    p27 = P2_13,
+
+    p38 = P0_4,
+    p39 = P0_5,
+    p40 = P0_10,
+    p41 = P0_11,
+    p42 = P2_0,
+    p43 = P2_1,
+    p44 = P2_2,
+    p45 = P2_3,
+    p46 = P2_4,
+    p47 = P2_5,
+    p48 = P2_6,
+    p49 = P2_7,
+    p50 = P2_8,
+    p51 = P2_10,
+    p52 = P2_11,
+    p53 = P2_12,
+#else
     p21 = P2_5,
     p22 = P2_4,
     p23 = P2_3,
@@ -65,13 +91,19 @@ typedef enum {
     p28 = P0_10,
     p29 = P0_5,
     p30 = P0_4,
+#endif
 
     // Other mbed Pin Names
 #ifdef MCB1700
     LED1 = P1_28,
     LED2 = P1_29,
     LED3 = P1_31,
     LED4 = P2_2,
+#elif defined(TARGET_LPC1769)
+    LED1 = P0_22,
+    LED2 = P0_22,
+    LED3 = P0_22,
+    LED4 = P0_22,
 #else
     LED1 = P1_18,
     LED2 = P1_20,
@@ -113,8 +145,8 @@ typedef enum {
     I2C_SDA0 = NC,
     I2C_SCL1 = p10,
     I2C_SDA1 = p9,
-    I2C_SCL2 = p27, // pin used by application board
-    I2C_SDA2 = p28, // pin used by application board
+    I2C_SCL2 = P0_11, // pin used by application board
+    I2C_SDA2 = P0_10, // pin used by application board
     I2C_SCL = I2C_SCL2,
     I2C_SDA = I2C_SDA2,
 } PinName;

targets/TARGET_NXP/mbed_rtx.h

@@ -50,7 +50,7 @@
 #define INITIAL_SP              (0x02009000UL)
 #endif
 
-#elif defined(TARGET_LPC1768)
+#elif defined(TARGET_LPC1768) || defined(TARGET_LPC1769)
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x10008000UL)

targets/targets.json

@@ -244,6 +244,10 @@
         "device_name": "LPC1768",
         "bootloader_supported": true
     },
+    "LPC1769": {
+        "inherits": ["LPC1768"],
+        "device_name": "LPC1769"
+    },
     "ARCH_PRO": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M3",

tools/export/iar/iar_definitions.json

@@ -110,6 +110,9 @@
     "LPC1768": {
         "OGChipSelectEditMenu": "LPC1768\tNXP LPC1768"
     },
+    "LPC1769": {
+        "OGChipSelectEditMenu": "LPC1769\tNXP LPC1769"
+    },
     "STM32F446RE": {
         "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE"
     },